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The Verilog synthesis now lowers power expressions with constant rhs to the equivalent multiplication.

The Verilog synthesis now lowers power expressions with constant rhs to the
equivalent multiplication.
@kroening kroening marked this pull request as ready for review September 16, 2024 23:03
@tautschnig tautschnig merged commit 2a0e75f into main Sep 17, 2024
@tautschnig tautschnig deleted the power2 branch September 17, 2024 07:41
Romy15200 pushed a commit to Romy15200/nws that referenced this pull request Aug 19, 2025
Verilog: synthesis for power expressions with constant rhs
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3 participants