SystemVerilog: conversion from/to packed union #738
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tautschnig
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Sep 30, 2024
| } | ||
| else if(dest.id() == ID_union) | ||
| { | ||
| // We use the first field of the union. |
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Just curious: does Verilog require that all fields have the same width? If not, could there be any problems if the first field wasn't sufficiently wide?
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Yes, in Verilog packed unions all fields must be the same width. Will add comment to say so.
| { | ||
| auto new_type = | ||
| unsignedbv_typet{numeric_cast_v<std::size_t>(get_width(type))}; | ||
| expr = typecast_exprt{expr, new_type}; |
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Will this reach our back-end? I don't think we'd support casts from a union. I suspect we'd need an extractbits here instead.
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Yes, the synthesis stage turns these into a member expression -- will add comment.
This adds conversions from/to packed unions to/from vector types.
tautschnig
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Sep 30, 2024
Romy15200
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Aug 19, 2025
SystemVerilog: conversion from/to packed union
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This adds conversions from/to packed unions to/from vector types.