PyStim is a lightweight SystemVerilog library that facilitates seamless integration between SystemVerilog and Python by embedding the Python interpreter directly into SystemVerilog.
PyStim allows developers to:
- Expose Python functions, classes, and objects to SystemVerilog with minimal boilerplate code
- Easily create SystemVerilog bindings for existing Python codebases
- Use a simple and intuitive API leveraging modern object-oriented patterns
- Handle type conversions between Python and SystemVerilog effortlessly
- Execute embedded Python code from within SystemVerilog
This integration enhances productivity and efficiency, especially in high-performance applications where the flexibility of Python complements the hardware-oriented nature of SystemVerilog.
- Minimal boilerplate for creating Python-SV bindings
- Support for advanced Python embedding
- Clean, modern API design
- Type-safe interactions between Python and SystemVerilog
- Ideal for simulation, testing, and hardware-software co-design workflows
- Download: pystim.dev
- Home Page: pystim.dev
- Installation Guide: docs.pystim.dev/installing.html
- API Reference: api.pystim.dev
- Documentation: docs.pystim.dev
We welcome any feedback, issues, or contributions to improve PyStim. Feel free to open an issue or pull request — your input helps make the library better for everyone!
Enjoy using PyStim and bridging the best of Python and SystemVerilog!