ppc64-QVM: direct mov_sx_rx via mtvsrws+xscvspdp on POWER9+#392
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Replaces the stw+lfs memory round-trip with two register ops. The earlier mtvsrwz attempt failed because that instruction writes word element 1 of the VSR while xscvspdp reads word element 0; mtvsrws splats the GPR into all four word elements so the bit pattern is also at element 0. Gated behind USE_ISA_3_0; older CPUs keep the memory path.
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@ec- this one is ready for review |
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Replaces the stw+lfs memory round-trip with two register ops. The earlier mtvsrwz attempt failed because that instruction writes word element 1 of the VSR while xscvspdp reads word element 0; mtvsrws splats the GPR into all four word elements so the bit pattern is also at element 0.
Gated behind USE_ISA_3_0; older CPUs keep the memory path.
Currently being tested. Please do not review.