fix(electronics): schematic T-tap connectivity (no false shorts, no crossing merges)#234
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…eparate Building a dense ESC by clicking surfaced a third issue: every net collapsed into one. The schematic net inference connected pins only at *coincident wire endpoints* — there was no point-on-segment test at all, so you couldn't tap a bus (a pin or wire-end landing on another wire's interior silently didn't connect), and the only way to join pins was to hit exact endpoints. Add a point-on-segment pass to generate_netlist: a pin, junction, or wire endpoint lying on another wire's interior joins that wire's net (T-taps / bus taps). It is deliberately point-vs-segment, never segment-vs-segment, so two wires that merely cross — with no pin, junction, or endpoint at the intersection — stay on separate nets. An explicit junction dot at a crossing still connects, as before. Tests: tap_onto_wire_interior_connects (bus tap joins) and crossing_wires_stay_separate (crossing does not merge); all 28 vcad-ecad-schematic tests pass, clippy clean. WASM rebuilt. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Same-named labels and one-pin power symbols (VCC/GND/+5V...) now merge into one net across the whole sheet without an explicit wire — the standard "global label / power port" behaviour. Drop a VCC symbol anywhere and it's on the VCC net; label two wires "PHASE_A" and they join. This keeps power rails sane on a dense board instead of hand-wiring a rail through every pin (exactly where the ESC shorted). In generate_netlist, after wire/tap connectivity, union all points that share a net name: label names plus the value of any one-pin power-type symbol. Power-port names also name the resulting net. Tests: power_ports_merge_by_value, same_name_labels_merge; 30 vcad-ecad-schematic tests pass, clippy clean. WASM rebuilt. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Electronics was the only major workspace not reachable from the top tab row — you entered it through a "PCB" button buried under Create, then it sprouted its own separate bottom toolbar. Promote it to a first-class "Circuit" tab (between Assembly and Simulate) and move the PCB-board entry there. First step toward consolidating the electronics tools into one consistent, discoverable place. - ToolbarTab += "circuit"; indigo tab color / theme / description - getAllTabs() lists Circuit (Circuitry icon) - the PCB-board tool moves from Create -> Circuit tsc + core build clean; verified live — the Circuit tab renders and shows the PCB Board tool. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
The component palette was a row of unlabeled icons — you couldn't tell the MCU from the regulator without hovering each one. Replace it with a vertical labeled list (icon + part name) behind a search box that filters by name / id / prefix / value, so finding a part is type-and-click. Builds on the reactive-library + a11y fixes. tsc + app build clean; verified live — the search box and labeled parts render in the Components panel. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
"Start blank / empty canvas" called addPrimitive("cube") — it dropped a
cube onto whatever was already open and never cleared an autosaved doc,
so returning sessions accumulated clutter (which bit me repeatedly while
building the ESC). Reset to a fresh empty document instead, matching the
"empty canvas" label.
tsc clean.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
The wire-snap highlight showed *where* you'd connect but not *what* — and the ESC's transistor C/E pins are close enough that you grab the wrong one and short the rails. Surface the snapped pin's identity (ref.pin, e.g. "Q1.C") and the net it's already on right at the cursor, so a wrong pin or an unintended short is visible before you click. snapToGridOrPin now returns the component ref + pin number; the snap indicator renders them plus getNetForPin(). tsc + app build clean. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Collapse a multi-line `.iter().any()` to one line so `cargo fmt --check` passes in CI. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Collapse the crossing-wires assertion and wrap the make_power signature so `cargo fmt --check` passes in CI. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
feat(electronics): UX pass — global nets, Circuit tab, searchable palette, blank reset
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Why
Third issue found dogfooding the "build an ESC by clicking" exercise: wiring a dense circuit made every net collapse into one giant short.
Root cause: the schematic net inference (
generate_netlist) connected pins only at coincident wire endpoints — there was literally no point-on-segment test. Two consequences:Fix
Add a point-on-segment pass to
generate_netlist: a pin, junction, or wire endpoint lying on another wire's interior joins that wire's net (T-taps / bus taps).It's deliberately point-vs-segment, never segment-vs-segment — so two wires that merely cross, with no pin/junction/endpoint at the intersection, stay on separate nets. An explicit junction dot at a crossing still connects, exactly as before. This is the standard EDA connectivity model and matches the requested behavior ("T-taps connect, crossings don't merge").
Tests
tap_onto_wire_interior_connects— a pin on a vertical bus joins the net.crossing_wires_stay_separate— a horizontal and a vertical wire that cross with nothing at the intersection stay on different nets.vcad-ecad-schematictests pass (incl. the existingjunction_merges_wires,single_wire_connects_two_pins);cargo clippyclean. WASM rebuilt (binary only — no binding/API change).Context
Third in a UX pass driven by building an ESC by clicking. Stacked on #233 (palette + a11y) and #232 (view toggle).
🤖 Generated with Claude Code