VOCS: Volitas Optical Circuit Switch

An open-source N x N chip-scale transparent optical circuit switch built from piezoelectric ScAlN phase shifters, with a nonvolatile ferroelectric variant whose coercive threshold doubles as a selector-free matrix-addressing mechanism.

Status: design stage, unmeasured. The layouts generate, verify and pass DRC (see below) but no silicon has been fabricated and the phase shifter as drawn has a known efficiency gap that the design must close before it works. This repo is honest about that: read docs/TECH_REVIEW.md before anything else. This project is released as open hardware in part as a defensive publication so the ideas below stay free for everyone.

The idea

Light enters on N fibres, passes through an N-column odd-even transposition fabric of 2x2 Mach-Zehnder bar/cross switches and exits on N fibres: any input to output permutation, fully transparent, no optical-electrical conversion, bitrate and protocol agnostic.

Each 2x2 element contains one piezoelectric phase shifter: a bottom electrode, a sputtered ScAlN film (11 percent Sc, 300 nm in the drawn cell) and an aluminum top electrode over the waveguide. Piezo elements are capacitors, which buys three things thermo-optic fabrics cannot have:

1. Near-zero hold power. Leakage only, nanowatts per element, versus roughly 20 mW per element continuously for heaters (a 32x32 thermal fabric burns about 10 W just holding state).
2. Nanosecond-class actuation, mechanically limited, versus milliseconds for the MEMS mirror switches deployed in datacenters today.
3. Matrix addressing. Capacitive elements sit at row/column intersections like LCD pixels: 31 pads drive the 120-element 16-port fabric, 63 pads drive the 496-element 32-port fabric.

The most interesting variant is ferroelectric. Above roughly 27 percent Sc the ScAlN film is ferroelectric, so an element latches in the bar or cross state and holds it at literally zero power, across power loss. The coercive field also acts as a built-in write selector: drive the selected row and column to opposite half-voltages so only the selected element exceeds the coercive voltage. No diode, no transistor, no per-element selector of any kind. To our knowledge a ferroelectric-coercive-threshold matrix write of photonic elements has not been published elsewhere; it is disclosed here (June 2026) so that it remains unpatentable by anyone.

The honest physics

The drawn 100 um unreleased actuator will not reach a pi phase shift at survivable voltage. Published unreleased AlN shifters sit near 240 V cm; released piezo-optomechanical structures reach 0.15 V cm. The gap is one to two orders of magnitude and the fixes are known: release the actuator with an undercut etch, raise the Sc fraction to about 30 percent, drive push-pull and optionally fold the waveguide under a longer electrode. A released push-pull element a few hundred micrometres long plausibly lands at a Vpi of 5 to 20 V. The full analysis with literature numbers and sources is in docs/TECH_REVIEW.md.

What is actually verified

Every generated chip self-checks before it writes:

• one top cell, no dangling references
• the waveguide layer is a single connected component containing every grating-coupler and port polygon (light can physically get from any input to any output)
• headless KLayout DRC, 15 rules covering waveguide, grating, Ge, piezo stack enclosures, metals, vias and pads: CLEAN on both reference chips
• the control-plane router proves 1000 random permutations each at N = 16 and N = 32, all routed in at most N columns

Reference chip	Elements	Columns	Pads
VOCS-16	120	16	31
VOCS-32	496	32	63

Quickstart

python -m venv .venv && . .venv/bin/activate
pip install -r requirements.txt
python ocs_gen.py --ports 16 --drc     # generates + verifies + DRC
python control/route_permutation.py    # router self-test

Generation takes seconds. Open the resulting .gds in KLayout.

Files

• ocs_gen.py generator and self-verification entry point
• switch_element.py 2x2 MZI element (386 um), ScAlN shifter cell, grating coupler and bond pad
• fabric_router.py fabric placement, rail routing, dual GC banks and the passive-matrix electrical routing (M2 columns x M1 rows)
• control/route_permutation.py switch-state router and fabric simulator (odd-even transposition sort)
• pdk.py internal AIM-aligned layer map with a remap point for real foundry layers; drc/ocs.drc (KLayout desktop) and drc/run_drc.py (headless)
• vocs_16port_*.gds, vocs_32port_*.gds pre-generated reference layouts

Topology note

Odd-even transposition (N columns, zero waveguide crossings) was chosen over Benes (2 log2 N - 1 columns but butterfly wiring full of crossings) because no measured low-loss crossing cell exists here. At N = 32 that trades about 23 extra element stages for zero crossings. Revisit once a characterised crossing is available.

Wanted: collaborators

This is a solo side project released so it can find the people it needs. Concretely useful:

• A group with MPW access (CORNERSTONE, Europractice, SiEPIC openEBL or similar) interested in taping out the shifter test structures or a small fabric. The passives work on any SOI-220 run; the piezo stack is a post-process module.
• ScAlN deposition at 25 to 40 percent Sc (BAW/piezoMEMS labs do these films routinely). The ferroelectric latching measurement is a first-demonstration-grade result waiting for a film.
• Measurement time on a fibre-coupled photonics bench.
• Design review, corrections to the physics analysis and foundry rule decks are all welcome as issues or PRs.

If any of this is you: open an issue.

License and citation

Apache License 2.0 (includes an explicit patent grant; see LICENSE). If this work is useful in research, cite it via CITATION.cff.