MEng Student — Electrical & Computer Engineering
Aristotle University of Thessaloniki · Thessaloniki, Greece
Fifth-year MEng student at AUTH, completing a degree that covers software systems, machine learning, and digital hardware design. Project work to date spans full-stack web development with CI/CD, applied ML and computational intelligence, and RTL design targeting FPGA.
Software & Web Development
Python · Java · C/C++ · JavaScript · HTML/CSS · React · Node.js · Express · Flask · MySQL · SQL
Machine Learning & Data
TensorFlow · Keras · scikit-learn · NumPy · MATLAB
Hardware & Systems
Verilog · SystemVerilog · Simulink · FPGA · VLSI · SVA
Tools & Workflows
Git · GitHub Actions · CI/CD · Agile · LaTeX
Full-Stack Web Application with CI/CD · Code
Node.js/Express REST API with React frontend, deployed on Render. Testing pipeline covers unit, integration, Cypress E2E, and k6 performance tests; CI/CD automated via GitHub Actions with Agile sprint management on Cyclopt.
Escape Room Management System · Code
MySQL relational schema with integrity constraints, role-based privileges, and SQL views. Flask web application with full CRUD functionality across three user roles: players, game masters, and managers.
AAC Audio Codec · Code
Python encoder/decoder pipeline implementing MDCT filterbank analysis/synthesis, Temporal Noise Shaping, psychoacoustic masking-based quantization, and Huffman entropy coding with variable-bitrate codebook selection.
IEEE 754 Floating-Point Multiplier · Code
2-stage pipelined single-precision multiplier in SystemVerilog with normalization, 6 rounding modes, and full exception handling. Correctness verified across all rounding modes and corner cases using SVA concurrent assertions on status flags.
Computational Intelligence Systems · Code
Mamdani and TSK Fuzzy Logic Controllers in MATLAB/Simulink for DC motor speed regulation and autonomous navigation. ANFIS models built for regression (airfoil noise prediction) and classification (epileptic seizure detection) using grid/subtractive partitioning and cross-validation.
Multi-Cycle RISC-V Processor · Code
Full RISC-V datapath in Verilog supporting R/I/S/B-type instructions, 32-register file, and a 5-state FSM control unit (IF/ID/EX/MEM/WB). Deployed on FPGA as a functional accumulator calculator with button-driven input.
Image Classification on CIFAR-10 · Code
CNN architectures in TensorFlow/Keras for 10-class image classification. Benchmarked against KNN, Nearest Centroid, and SVM baselines with systematic performance analysis and documentation.
Numerical Optimization Methods · Code
MATLAB implementation of Steepest Descent, Newton's Method, and Levenberg-Marquardt across multiple objective functions. Extended to constrained optimization via projected gradient methods; Genetic Algorithms applied to a network traffic flow minimization problem under capacity constraints.
