This project implements a 6-bit comparator system capable of comparing two inputs in both signed (2’s complement) and unsigned modes. The design is built using structural Verilog, relying only on basic logic gates with specified delays to simulate real hardware behavior.
The system takes two 6-bit inputs (A and B) along with a selection signal (S) to determine the comparison type. It produces three outputs: Equal, Greater, and Smaller, indicating the relationship between the inputs. To ensure stable and synchronized operation, D flip-flops are used at both input and output stages.
The project includes:
Structural implementation of unsigned and signed comparators A behavioral model for verification A complete testbench that checks all input combinations Timing analysis with a maximum operating frequency of approximately 5.92 MHz Verification through intentional fault injection to validate correctness
Simulation results highlight the importance of gate delays, synchronization, and timing stability in digital design. The project was developed and tested using Active-HDL, providing hands-on experience in building and verifying digital systems at the gate level.