Code in Verilog for a Dual Binary and Grey Code Converter in Verilog code, as well as implementation on a Nexys-A7 100T. User is able to input 4-bit data that can be translated into binary or grey code based on the 'sel' data, where a logic level '0' would make your input in binary and the output would be in grey code while a 'sel' data with logic level '1' would make your input in grey code and the output would be in binary. Implementation on the Nexys-A7 100T makes the 4 right most switches on the Nexys-A7 100T your input and the 4 right most LEDS on the Nexys-A7 100T your output.
- Binary to Grey Code logic
- The Most Significant Bit (MSB) of the gray code will be equal to the MSB of the given binary number. The second MSB of the gray code will be XOR of the first and second MSB of the given binary number. The third MSB of the gray code will be XOR of the second and third MSB of the given binary number. The binary number to gray code conversion continues with this pattern.
- Grey Code to Binary logic
- The MSB of the binary number will be equal to the MSB of the given gray code. The second MSB of the binary number will be XOR of the first MSB of the binary number and the second MSB of the given gray code. The third MSB of the binary number will be XOR of the second MSB of the binary number and the third MSB of the given grey code. The grey code to binary number conversion continues with this pattern.
- Hands‑On FPGA Implementation
- Uses Nexys A7 board switches for inputs and the led displays for outputs.
- Xilinx Vivado 2022.2
- Verilog HDL
- Nexys A7-100T
- Real FPGA deployment with hardware-level testing
- Builds intuition for debugging
- Builds knowledge on Binary to Grey Code conversion
Edgar Restor