LiteX M2SDR 2026_05_15

2026-05-15 First Date-Named Release

Feature Status at Release

• Release artifacts: first date-named, timing-checked archives are provided for the supported core M.2 PCIe and Acorn Baseboard Ethernet images, with CSR exports and per-build manifests.
• M.2 PCIe: PCIe Gen2 x1 and x2 images are provided for the M.2 form factor; PCIe-only images keep the 125MHz system clock.
• Baseboard Ethernet: 1000BaseX Etherbone control and LiteEth UDP RX/TX sample streaming are supported on the Acorn Baseboard Mini.
• Baseboard PCIe + Ethernet: a combined PCIe Gen2 x1 + 1000BaseX Ethernet image is provided and uses a 100MHz system clock for timing margin.
• Ethernet PTP: the baseboard Ethernet PTP image disciplines the board time_gen clock for timestamps, PPS, and host-visible board time.
• PTP RFIC reference: the dedicated baseboard PTP RFIC-reference image exposes the FPGA clk10 MMCM discipline loop and SI5351C FPGA-fed 10MHz input mode.
• Host software: libm2sdr, m2sdr_util, SoapySDR, m2sdr_play, and the FM helper utilities include the matching Ethernet/PTP/RFIC-reference controls and examples.
• Source-build options: White Rabbit, SATA, VRT, 2.5G Ethernet, PCIe x4, and oversampling images remain available from source but are outside this first release artifact set.