feature(dcd_dwc2) : Added cache synchronization on esp32p4 while DMA is used

[roma-jam]

Requirements

1. To enable Buffer DMA mode, esp-tinyusb changes should be done (define CFG_TUD_DWC2_DMA and implement CFG_TUSB_MEM_SECTION, refer feature(esp_tinyusb): Added mode configuration for dcd_dwc2 layer esp-usb#88)
2. Support Buffer DMA mode for ESP32S2/S3 (no sync required, so this could be achieved with step 1.) and ESP32P4 (sync required, changes in this PR is crucial for Buffer DMA on P4) chips.

Measurements

Measurements were made on tusb_msc example (read-write operations benchmark, SDMMC target).

ESP32S3

MSC Buffer size (bytes)	Slave Mode (R/W)	Buffer DMA (R/W)
512	463,5 kB/s / 161,1 kB/s	512,6 kB/s / 171,2 kB/s
4096	733,5 kB/s / 452,9 kB/s	878,8 kB/s / 469,9 kB/s
8192	N/A / N/A	N/A / N/A

ESP32P4

MSC Buffer size (bytes)	Slave Mode (R/W)	Buffer DMA (R/W)
512	909,6 kB/s / 217,8 kB/s	942,8 kB/s / 222,6 kB/s
4096	932,7 kB/s / 225,2 kB/s	3,8 MB/s / 1,1 MB/s
8192*	934,4 KB/s / 229,4 KB/s	5,3 MB/s / 1,8 MB/s

*Benchmark results provided

Limitations

Not working:

• tusb_ncm (S2/S3, TinyUSB stack overflow during recv_transfer_datagram_to_glue_logic())

Working examples:

• tusb_composite_msc_serial
• tusb_console
• tusb_hid
• tusb_midi
• tusb_msc
• tusb_serial_device (verified tx with len = [1..512])

Breaking change

No breaking changes

Checklist

• Pull Request name has appropriate format (for example: "fix(dcd_dwc2): Resolved address selection when several phy are present")
• Optional: README.md updated
• CI passing

Related issues

No related issues

[roma-jam]

@tore-espressif @peter-marcisovsky
This is a (preliminary version with using cache sync) DMA support for P4.
There are couple of changes, regarding the MSC and CDC class drivers, so let me know if it is better to move them out to another PR.

DMA requires the specific configuration by esp-tinyusb component, so the link to the changes: espressif/esp-usb#88

[tore-espressif]

Just a few work-in-progress comments/questions

[tore-espressif]

I don't understand the terminology used in this PR.

What does it mean 'cache is enabled'? We sure don't want to enable/disable the cache for all RAM access system wide...

[roma-jam]

It more like about the way, how we want to handle the memory. while DMA is used.
I thought, that there will be an option to choose between:

• Use cache and synchronize it explicitly in dcd_dwc2
• Bypass cache and use direct-access addresses

[roma-jam]

This PR is not relevant anymore, as the cache support were implemented in upstream based on the partial commit from here (hathach#2877)
The device classes modifications for buffer alignment and memory sections is in the upstream PR: hathach#2884

So far, temporary changes in class device (cdc and mscd) are not significant, as they will be covered by the merging the PR above.

[peter-marcisovsky]

@roma-jam sorry for the late review, I see, it closed now..