This is the repository for the computer architecture group assignments and project.
Contains the code for a cache implementation.
Contains the code for a MIPS 32 bit pipelined processor
Contains the code for an optimized processor. We have opted to implement a cached memory access scheme. Instead of a data memory and instruction memory, we will have a split cache.
In order to test this, we will run a series of instructions, and benchmark programs before and after the optimizations.