Bump GCC pin in faiss-gpu conda recipe to fix AVX2 SIMD miscompilation#5125
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Bump GCC pin in faiss-gpu conda recipe to fix AVX2 SIMD miscompilation#5125algoriddle wants to merge 1 commit into
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Summary:
The faiss-gpu conda recipe pins `{{ compiler('cxx') }} =12.4` (GCC 12.4). GCC 12.4 miscompiles the 16-bin SIMD histogram reduction in `partitioning_simdlib256.h`, producing correct results for bins 0-7 but near-zero for bins 8-15. This causes `test_16bin_bounded_bigrange` in `TestHistograms_AVX2` to fail in the CUDA 12.6 GPU nightly.
The bug is in GCC 12's code generation for the AVX2 cross-lane reduction chain (`_mm256_hadd_epi16` → `_mm256_permute2f128_si256` → `_mm256_permutevar8x32_epi32`). GCC 13 and 14 both compile this correctly. The CPU-only `faiss/meta.yaml` leaves the compiler unpinned (gets GCC 14), which is why only the GPU nightly fails.
The GCC 12.4 pin was introduced in D84193438 as part of a batch nightly fix — not a deliberate CUDA compatibility constraint. CUDA 12.6 supports up to GCC 13.x as host compiler (GCC 14 requires CUDA 12.9+), so we widen the pin to `>=12.4,<14`.
Reproduced locally: GCC 12.4 fails, GCC 13.4 passes, GCC 14.2 passes — all on the same faiss source, same test, same machine.
Differential Revision: D101601476
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@algoriddle has exported this pull request. If you are a Meta employee, you can view the originating Diff in D101601476. |
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This pull request has been merged in 6e64c5d. |
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Summary:
The faiss-gpu conda recipe pins
{{ compiler('cxx') }} =12.4(GCC 12.4). GCC 12.4 miscompiles the 16-bin SIMD histogram reduction inpartitioning_simdlib256.h, producing correct results for bins 0-7 but near-zero for bins 8-15. This causestest_16bin_bounded_bigrangeinTestHistograms_AVX2to fail in the CUDA 12.6 GPU nightly.The bug is in GCC 12's code generation for the AVX2 cross-lane reduction chain (
_mm256_hadd_epi16→_mm256_permute2f128_si256→_mm256_permutevar8x32_epi32). GCC 13 and 14 both compile this correctly. The CPU-onlyfaiss/meta.yamlleaves the compiler unpinned (gets GCC 14), which is why only the GPU nightly fails.The GCC 12.4 pin was introduced in D84193438 as part of a batch nightly fix — not a deliberate CUDA compatibility constraint. CUDA 12.6 supports up to GCC 13.x as host compiler (GCC 14 requires CUDA 12.9+), so we widen the pin to
>=12.4,<14.Reproduced locally: GCC 12.4 fails, GCC 13.4 passes, GCC 14.2 passes — all on the same faiss source, same test, same machine.
Differential Revision: D101601476