Backport T2S template fix to v1.2 #3936
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We updated the fingerprint files in PR firecracker-microvm#3813, since Intel microcode release (microcode-20230512) changed to set IA32_ARCH_CAPABILITIES.RRSBA (bit 19) to 1 on Intel CascadeLake CPU. The mitigation itself is already in place which is eIBRS. Since the kernel enables eIBRS by default using SPECTRE_V2_EIBRS mode regardless of the IA32_ARCH_CAPABILITIES.RRSBA bit, hosts and guests should not get impacted by this change. However, it has a role to inform softwares whether the part has the RRSBA behavior. The T2S template has set it to 0 explicitly before, but this commit changes to set it to 1 so that guest kernels and applications can know that the processor has the RRSBA behavior. The reason why it sets the bit to 1 instead of passing through it from the host is that it aims to provide the ability to securely migrate snapshots between Intel Skylake and Intel CascadeLake. Signed-off-by: Takahiro Itazuri <itazur@amazon.com>
kalyazin
approved these changes
Jul 5, 2023
roypat
approved these changes
Jul 5, 2023
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Changes
Reason
An Intel microcode update set IA32_ARCH_CAPABILITIES.RRSBA to 1 on CascadeLake, which requires revision of T2S templates that have already been released.
Since T2CL template is not included in v1.2, the commit for T2CL does not need to be backported.
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CONTRIBUTING.md.PR Checklist
[ ] If a specific issue led to this PR, this PR closes the issue.[ ] Any required documentation changes (code and docs) are included in this PR.[ ] API changes follow the Runbook for Firecracker API changes.CHANGELOG.md.[ ] NewTODOs link to an issue.rust-vmm.