Summary
Add Pins IR model and XDC constraint emitter in specs/pins/, replacing the hardcoded XDC in bootstrap/src/main.rs.
Deliverables
specs/pins/ir.t27 — IR model (PinLocation, IoStandard, SignalReference, Binding, Design, ClockDef) + conflict detection invariantsspecs/pins/emitter_xdc.t27 — XDC generator with emit_pin, emit_clock, emit_header, qmtech_xc7a100t_minimal() presetspecs/pins/OWNERS.md — Domain ownership
Why
Board constraints are currently hardcoded in Rust (main.rs line ~3231). Moving to structured .t27 specs enables:
- Machine-validated pin assignments (no LOC conflicts, all clocks bound, no orphans)
- Board profile selection via
--profile minimal / --profile full
- Future integration with
t27c fpga-build to generate XDC from .t27 board specs
Key invariants
has_pin_conflict(design) — no two bindings share a package pinhas_port_conflict(design) — no two bindings share a port+indexall_clock_ports_bound(design) — every clock binding has a ClockDef
Related: #381 (board profiles), #383 (roadmap), #367 (FPGA pipeline)
Summary
Add Pins IR model and XDC constraint emitter in
specs/pins/, replacing the hardcoded XDC inbootstrap/src/main.rs.Deliverables
specs/pins/ir.t27— IR model (PinLocation, IoStandard, SignalReference, Binding, Design, ClockDef) + conflict detection invariantsspecs/pins/emitter_xdc.t27— XDC generator with emit_pin, emit_clock, emit_header, qmtech_xc7a100t_minimal() presetspecs/pins/OWNERS.md— Domain ownershipWhy
Board constraints are currently hardcoded in Rust (main.rs line ~3231). Moving to structured .t27 specs enables:
--profile minimal/--profile fullt27c fpga-buildto generate XDC from .t27 board specsKey invariants
has_pin_conflict(design)— no two bindings share a package pinhas_port_conflict(design)— no two bindings share a port+indexall_clock_ports_bound(design)— every clock binding has a ClockDefRelated: #381 (board profiles), #383 (roadmap), #367 (FPGA pipeline)