TRI-NET cross-line package: P0 NMSE / P1 API+whitepaper / P2 22FDX projection + Zenodo bundles

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Cross-line TRI-NET package — P0/P1/P2 next-lineup improvements

This is the umbrella tracking issue for the next batch of TRI-NET line-level
deliverables in t27 (the spec-first toolchain + numeric format registry
product of the line). The work below is docs-and-specs only in t27 —
no gen/ edits, no new *.sh on the critical path, no silicon claims
beyond what already exists in STATUS.md.

The TRI-NET line is composed of t27 plus the three sibling chip repos
(tt-trinity-phi, tt-trinity-euler, tt-trinity-gamma); see
LINEUP.md for the four-product map. This issue tracks documents and
schemas that live in this repo and link out, where applicable, to those
chip repos.

Deliverables

P0 — GF16 vs bfloat16 NMSE standard comparison protocol

• New doc: docs/GF16_BFLOAT16_NMSE_PROTOCOL.md
• New machine-readable spec: specs/benchmarks/gf16_bfloat16_nmse.t27
• New JSON schema for results manifest: schemas/nmse-protocol-v1.json
• Spec must contain test / invariant / bench per L4 TESTABILITY.

P1 — TRI-NET API for external integration

• New doc: docs/TRI_NET_API.md
• New .t27 spec: specs/api/tri_net_api.t27
• New JSON schema: schemas/tri-net-api-v1.json
• Schema must be conservative — describe SHAPE of an external integration
  interface, not promise silicon behaviour.

P1 — TRI-NET whitepaper / value proposition

• New doc: docs/TRI_NET_WHITEPAPER.md — open high-assurance ternary AI
  silicon substrate framing; cross-links to LINEUP.md,
  COMPETITORS.md, STATUS.md, BENCHMARKS.md, FORMAT_REGISTRY.md.

P2 — 22FDX TOPS/W projection methodology

• New doc: docs/22FDX_TOPS_W_PROJECTION.md
• Clearly labelled projection, not measured silicon, with assumptions
  and confidence levels. Cross-link to chip repos tt-trinity-euler and
  tt-trinity-gamma where 22FDX targeting is plausible-future, not
  promised.

P2 — Zenodo bundles plan for TRI-NET v1–v3

• New doc: docs/ZENODO_BUNDLES.md
• Manifest / checklist only — no fabricated DOIs. Existing
  DOI 10.5281/zenodo.19227877 (cited in NOW.md) is referenced as v0
  baseline; v1–v3 are planned bundles whose DOIs are issued only at
  upload time.

Cross-links

• P0 D2D protocol spec lives in tt-trinity-euler / tt-trinity-gamma
  (chip repos). t27 surfaces only the toolchain-side hooks.
• Triple-Deck chip implementation references the W47/W48/W49 Coq lemmas
  already landed in this repo (trios-coq/Physics/ — see docs/NOW.md),
  while the silicon-side Triple-Deck implementation lives in the chip
  repos.

Law compliance plan

• L1 TRACEABILITY — this issue exists; PR must say Closes #N.
• L2 GENERATION — no gen/ edits.
• L3 PURITY — all new Markdown ASCII / English; Cyrillic check must
  pass (scripts/check_first_party_doc_language.py).
• L4 TESTABILITY — new .t27 specs contain test / invariant /
  bench blocks.
• L5 IDENTITY — phi^2 + 1/phi^2 = 3 cited verbatim where relevant.
• L6 CEILING — FORMAT-SPEC-001.json and gf16.t27 are referenced
  as SSOT; no new numeric kernel claims.
• L7 UNITY — no new *.sh.

Out of scope

• Silicon-measured TOPS/W numbers (these never appear unless backed by
  direct device evidence).
• D2D protocol implementation (chip repos own this).
• Fabricated or pre-allocated DOIs.

R5-HONEST posture

Every claim in the new docs is either backed by an in-repo artifact or
explicitly labelled as projection / planned. No silicon parity claim is
made against any commercial product.