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feat(pins): implement XDC emitter from Pins IR#380

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feat/pins-xdc-emitter
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feat(pins): implement XDC emitter from Pins IR#380
gHashTag wants to merge 3 commits intomasterfrom
feat/pins-xdc-emitter

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@gHashTag gHashTag commented Apr 8, 2026

Summary

Creates specs/pins/ domain with two .t27 specs:

ir.t27 — Pins IR model

  • PinLocation (name, bank), IoStandard (name), SignalReference (port, optional index)
  • Binding (signal + pin + iostandard + is_clock + clock_period_ns + pullup)
  • Design (name + bindings vector)
  • Predefined constants: LVCMOS33, LVCMOS18, LVDS25
  • 3 test blocks with invariants

emitter_xdc.t27 — XDC constraint generator

  • emit_pin(binding)set_property -dict { PACKAGE_PIN ... IOSTANDARD ... } [get_ports ...]
  • emit_clock(binding)create_clock -period ... -name ... [get_ports ...]
  • emit_design(design) → full Vivado XDC
  • emit_design_nextpnr(design) → nextpnr-compatible XDC (no unsupported commands)
  • qmtech_xc7a100t_minimal() → 12-binding preset matching working XC7A100T bitstream
  • 7 test blocks + 1 invariant (all pins non-empty)

Verification

t27c parse specs/pins/ir.t27        # OK
t27c parse specs/pins/emitter_xdc.t27  # OK
t27c gen-verilog specs/pins/ir.t27   # OK (struct/const Verilog output)
t27c seal --save specs/pins/ir.t27   # Sealed
t27c seal --save specs/pins/emitter_xdc.t27  # Sealed

Closes #367

gHashTag added 3 commits April 8, 2026 22:36
Add three layers of TRI tooling:

1. t27c subcommands: tri-status, tri-skill-begin/end, tri-cell-checkpoint/seal,
   tri-gen, tri-test, tri-verdict, tri-experience-save
2. Standalone 'tri' binary (cli/tri/) with full PHI LOOP workflow
3. MCP server (cli/tri-mcp/) exposing 10 tools via JSON-RPC 2.0 over stdio

Add GitHub Actions workflow for FPGA E2E build:
- fpga-smoke: Verilog generation only (fast, every PR)
- fpga-synthesis: Yosys synthesis + JSON netlist
- fpga-report: Summary of pipeline status

Closes #367
New specs/pins/ directory with:

- ir.t27: Pins IR model (PinLocation, IoStandard, SignalReference,
  Binding, Design) with test blocks for construction invariants
- emitter_xdc.t27: XDC constraint generator with:
  - emit_pin: set_property PACKAGE_PIN/IOSTANDARD for any Binding
  - emit_clock: create_clock for clock bindings
  - emit_design: full XDC output for a Design
  - emit_design_nextpnr: nextpnr-compatible format (no current_design,
    no set_false_path)
  - qmtech_xc7a100t_minimal(): 12-binding preset for XC7A100T board
  - 7 test blocks + 1 invariant (all pins non-empty)

Both specs parse and gen-verilog successfully. Sealed.

Closes #367
@gHashTag gHashTag force-pushed the feat/pins-xdc-emitter branch from d1b7069 to 4f493f5 Compare April 8, 2026 15:37
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gHashTag commented Apr 9, 2026

Superseded by #385 (Pins IR + XDC emitter) which is already merged with 21 tests, 7 invariants, and full conflict detection. This PR had an earlier, simpler version of the same specs.

@gHashTag gHashTag closed this Apr 9, 2026
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feat(fpga): MAC module in synthesis, &&/|| precedence fix, field access fix

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