ci(fpga): Verilog hash + synthesis regression checks

[gHashTag]

Summary

Closes #395

Add regression checks to the FPGA CI workflow for bit-for-bit reproducibility tracking.

Changes

• Smoke job: Per-file SHA256 + size table in GitHub job summary
• Synthesis job: synth.json size guard (warning if < 1000 bytes) + hash
• Both jobs now use --profile minimal flag
• Report section tracks hash+size across runs

Example output in job summary

| File | Size (bytes) | SHA256 (first 16) |
|------|-------------|-------------------|
| mac.v | 1234 | a1b2c3d4e5f6a7b8 |
| uart.v | 2345 | ... |

Test plan

• fpga-build.yml syntax validated
• Local smoke test passes with --profile minimal
• Local synthesis passes with --profile minimal