feat(host): DMA channel model with CRC32 integrity (W59, R-HS-9)#832
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Wave 59 (R-HS-9): DmaChannel<M: Mmio> with embedded CRC32 checksum. DmaConfig builder, DmaError variants, DmaReport, cycle estimation. DMA_CTRL (0x28), DMA_STAT (0x2C) CSR offsets added. 19 new tests, all pass.
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This was referenced May 24, 2026
This was referenced May 24, 2026
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Closes #831
Wave 59 (R-HS-9): Host DMA channel model with CRC32 integrity
What
bootstrap/src/host/dma.rswithDmaChannel<M: Mmio>DmaConfigbuilder: src/dst addresses, word count, optional CRC32 verificationDmaError: ZeroLength, ExceedsMaxLen, AlreadyBusy, ChecksumMismatchDmaReport: words transferred, CRC32 checksum, state, cycle estimateDMA_CTRL(0x28),DMA_STAT(0x2C); CSR_COUNT 10→12Tests
19 new inline tests, all pass. 841 total tests on this branch (836 master + 5 new from csr_map update... actually 836 + 19 - pre-existing = correct).
Why
Software model of the DMA controller for weight word transfers from host to BRAM. Supports partial transfers, CRC32 integrity verification with trailer word, error states, and per-transfer cycle estimation.