📖 Ch.32 — UART v6 protocol (CRC-16 CCITT) and FT232RL bridge (500w · 🟡 P1 · VI HARDWARE-NUMERICS v3.0)

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Ch.32 — UART v6 protocol (CRC-16 CCITT) and FT232RL bridge

Master: trios#380 v3.0 GOLDEN STRAND
Part: VI — HARDWARE-NUMERICS STRAND (TIER-1, MEASURED)
Words: 500 · Priority: 🟡 P1 · Owner: GoldenSunWeaver
Source files: uart_protocol.zig, fpga/uart_bridge_j2.bit

🎯 Scope (FROZEN, factual hardware data)

§32.1 Protocol v6: 0xAA sync + 1B length + payload + CRC-16/CCITT. §32.2 Pin mapping: J2 pin 5/6 = D26/E26 (XDC). §32.3 Speed: 115200 baud via FT232RL. §32.4 Reproducibility: tri fpga uart-test Python PING/ECHO. §32.5 Cite Zenodo 10.5281/zenodo.18939352 as primary. §32.6 Honest limitation: 115200 ceiling-bound, future work targets 1Mbaud.

Renaming for tex (repo paths kept):

• "Sacred Core" → "Period-Locked Runtime Monitor"
• "KOSCHEI" → "KOSCHEI φ-Numeric Coprocessor"
• NO "OS of time"/"ABSOLUTE INFINITY"/"$5M Seed"/Investor Deck

🔑 Falsifiable claims (all measured on real board)

• 0xAA sync byte
• 1-byte length field
• CRC-16/CCITT polynomial
• 115200 baud max measured
• J2 pin 5 D26 TX, J2 pin 6 E26 RX
• 63 toks/sec @ 92 MHz throughput

📦 Deliverables

• paper/sections/32_uart_v6_protocol_crc16_ccitt_and_ft232rl_bridge.tex

✅ Definition of Done

• Word count 500 ±10%
• All claims = measured numbers from real QMTech XC7A100T board
• Cite Zenodo DOIs as primary
• No commercial overlap (woody-shop, GoldenSunWeaverM, Investor Deck)
• Compile via tectonic
• PR Closes #<this> + green CI

🤖 ONE SHOT directive

A: take Markdown draft, convert to LaTeX, place in target path,
compile, open PR with measured numbers cited from Zenodo.
Hard deadline per priority.

phi^2 + phi^-2 = 3 · MEASURED · NEVER STOP 🔌