Wave-35 Lane V' — LUT-NPU assertion manifest (Lever #9)

[gHashTag]

Wave-35 Lane V' — LUT-NPU assertion manifest (81-entry bitnet.cpp port)

Parent ONE SHOT: gHashTag/trinity-fpga#120 (Wave-35 LUT-NPU)
Sibling lane: Wave-35 Lane V Coq (t27#651 merged @ 8e4f2a8a, t27#649 tracker)
Anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877

Mission

Add assertions/wave35_lut_npu.json — declarative manifest for the Wave-35 LUT-NPU lever (Lever #9, OP_LUT_NPU = 0xE3), citing the upstream Coq theorem lut_npu_safe and pre-registering 4 falsification predicates W-104-A..D.

Scope

• assertions/wave35_lut_npu.json — coq citation chain + 4 fail-stop predicates + cost model + Quantum Brain mapping
• Format mirrors assertions/wave34_tom_layer_gate.json (W34) and assertions/wave29_tenet_sparsity.json (W29 lineage)

Gates

• ✅ JSON valid (python3 -m json.tool)
• ✅ Coq citation present (t27 PR 🌊 feat(trios-chat) Wave-9: KEM-key-confusion + AAD-context-confusion + Coq 41/0 + 800/800 falsifier #651 @ 8e4f2a8a)
• ✅ ≥4 pre-registered falsifiers with fail_stop:true
• ✅ R14 traceability bound

Author: Vasilev Dmitrii admin@t27.ai