Use root relative paths and add verilog models#118
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ThomasPluck merged 2 commits intogdsfactory:feat/schematic-metadatafrom Mar 27, 2026
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Copied from IHP-Open-PDK so the PDK package is self-contained for ngspice simulation. These can be compiled to OSDI with openvaf. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Reviewer's GuideSwitches all SPICE device schematics to use root-relative model library paths under ihp/models/ngspice/models and adds Verilog-A model sources, headers, and documentation for MOS varactor, PSP103, and r3_cmc models for ngspice/Xyce integration. Flow diagram for schematic simulation using root relative ngspice model librariesflowchart TD
U[Designer] --> S1[Select device in ihp_cells]
S1 --> S2[Generate DSchematic with spice_type SUBCKT]
S2 --> S3[Set library field to ihp/models/ngspice/models/...lib]
S3 --> C1[Create simulation netlist]
C1 --> NG[Run ngspice]
NG --> L1[Resolve library path relative to project root]
L1 --> L2[Load model file from ihp/models/ngspice/models]
L2 --> SIM[Execute simulation]
SIM --> O[Waveforms and results]
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ThomasPluck
approved these changes
Mar 27, 2026
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Summary by Sourcery
Update SPICE model library references to use project-relative paths and vendor model directories, and add Verilog-A device model sources and supporting files for ngspice/XYCE integration.
New Features:
Enhancements: