ERROR: wire not found for $posedge

[stevenbell]

I've got a relatively simple code example with abnormal style which doesn't synthesize:

library IEEE;
use IEEE.std_logic_1164.all;

entity lfsr2 is
  port(
    clk : in std_logic;
    reset : in std_logic;
    b : out std_logic
  );
end lfsr2;



architecture synth of lfsr2 is


signal a : std_logic;
signal c : std_logic;

begin

  
process (clk) begin

    if reset = '1' then
        if rising_edge(clk) then
            b <= '1';
            c <= '1';
        end if;
    else
        if rising_edge(clk) then
            c <= a;
            b <= c;
        end if;
    end if;
    
end process;

a <= b xor c;

end;

Running yosys -m ghdl -p "ghdl --std=08 lfsr2; write_json netlist.json" gives:

 Yosys 0.9+3911 (git sha1 dcd9f0af, clang 7.0.1-8+deb10u2 -fPIC -Os)


-- Running command `ghdl --std=08 lfsr2; write_json netlist.json' --

1. Executing GHDL.
Importing module lfsr2.
ERROR: wire not found for $posedge

Currently using docker image (hdlc/ghdl - yosys - 189a1f80cd33).

[tgingold]

I am not sure this is accepted by synthesizer. Do you want it to be accepted or do you want a better error message ?

[stevenbell]

I don't particularly care -- it works in Lattice LSE and Synplify, so it seems like it should synthesize. But a descriptive message that explains the error would be fine with me.

My use case is that this is the backend for vhdlweb.com (a VHDL coding practice website), where I've got dozens of students learning VHDL and trying all sorts of bad code. If code doesn't synthesize for some reason, I want to give them something that explains why.

[albydnc]

I have got the same error, is there a way to get a better error message? maybe locating the fault?
Thanks