🧩 Constraint Solving POTD:Problem of the Day: SMT for Circuit Verification

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Problem Statement

SMT for Circuit Verification: Boolean Circuit Satisfiability

In circuit verification, we want to determine whether a given boolean circuit can produce a satisfying assignment — that is, can we find input values that cause a critical property to be violated?

Consider a 4-bit multiplier circuit that computes Z = X × Y where X, Y ∈ {0..15}. Suppose the specification requires that Z ≤ 200 for all valid inputs. Can an attacker find inputs where Z > 200 (revealing a circuit flaw)?

Input: A boolean circuit represented as a DAG of logic gates (AND, OR, NOT, XOR) and a safety property expressed as a constraint (e.g., output_bits ≤ threshold).

Output: Either a satisfying assignment (counterexample showing the property violation) or a proof that no such assignment exists.

Concrete Instance

Circuit: 
  a, b, c, d ∈ {0, 1}  (4-bit inputs)
  g1 = a AND b
  g2 = NOT c OR d
  g3 = g1 XOR g2
  
Property: g3 must always be 1 (safety invariant)

Question: Is there an input assignment that makes g3 = 0?

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Why It Matters

Hardware verification: Chip manufacturers use SMT solvers to verify CPU instruction decoders, ALUs, and memory controllers before tapeout. A single undetected bug can cost hundreds of millions in recalls.

Firmware security: Researchers apply SMT to find exploitable paths through cryptographic implementations and bootloaders, ensuring constant-time properties and preventing side-channel vulnerabilities.

Protocol verification: Network protocols and security handshakes are modeled as state machines and verified using SMT solvers to rule out authentication bypasses or encryption weaknesses.

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Modeling Approaches

Approach 1: Pure SAT Encoding

Convert the circuit and property to a satisfiability problem using Tseitin transformation:

• Decision variables: x_i ∈ {0, 1} for each input and gate output
• Constraints: Conjunctive normal form (CNF) clauses encoding each gate
  • g1 = a AND b → (¬a ∨ g1) ∧ (¬b ∨ g1) ∧ (a ∨ b ∨ ¬g1)
• Safety negation: Assert ¬property (add clause for property violation)

Trade-offs: Pure SAT is simple and highly optimized; modern SAT solvers (CaDiCaL, MapleSAT) handle millions of clauses. However, reasoning about arithmetic (e.g., Z ≤ 200) requires explicit bit-width expansion and can blow up clause count.

Approach 2: SMT (Satisfiability Modulo Theories)

Use an SMT solver (Z3, CVC5) with multiple theories:

• QF_BV (Quantifier-Free Bitvector): Direct encoding of bit-width arithmetic
• QF_UF (Quantifier-Free Uninterpreted Functions): Abstract gate logic
• QF_LIA (Linear Integer Arithmetic): Constraints like Z ≤ 200

Example pseudo-code:

(declare-fun a () (_ BitVec 4))
(declare-fun b () (_ BitVec 4))
(declare-fun z () (_ BitVec 8))

(assert (= z (bvmul a b)))
(assert (not (bvule z #x0C8)))  ; NOT (Z ≤ 200)

(check-sat)  ; Returns "sat" + counterexample if property violated

Trade-offs: SMT solvers combine SAT solving with theory-specific reasoning engines. Bitvector arithmetic is handled symbolically without full expansion, scaling much better for large bit-widths. However, more complex to optimize for specific domains.

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Key Techniques

1. Tseitin Transformation & CNF Normalization

Convert an arbitrary Boolean formula into CNF by introducing auxiliary variables for subexpressions. This reduces arbitrary circuits to a uniform clause structure but increases variable count. Modern SAT solvers handle this internally.

2. CDCL (Conflict-Driven Clause Learning)

When a conflict is discovered (unsatisfiable subproblem), the SAT solver learns a new clause capturing the reason for the conflict. Backjumping then skips over provably non-useful search branches. This is essential for circuit problems with thousands of gates.

3. Theory Propagation & Lazy Theory Splitting

SMT solvers interleave SAT solving with theory solving (e.g., arithmetic, bit-vector reasoning). When the SAT solver assigns variable values, theory solvers check consistency and propagate implications. If an inconsistency is found, a conflict clause is added, guiding the search.

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Challenge Corner

Can you model circuit verification without flattening the circuit to CNF?

One approach is to use constraint hierarchies or incremental SAT: build the SAT instance layer-by-layer (first primary inputs → gates → latches → outputs), reusing previous solver state. How would you structure the incremental queries to verify a sequential circuit (one with memory elements and state transitions)?

Extension: How would you extend this problem to handle probabilistic fault models where gates fail with low probability? This shifts from "Is property violated?" to "What is the probability of property violation under component faults?"

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References

1. Biere, A., Heule, M., van Maaren, H., & Walsh, T. (Eds.) Handbook of Satisfiability (2nd ed.). IOS Press, 2021.

   • Authoritative reference for SAT solvers, SMT, and applications to hardware verification.

2. de Moura, L., & Bjørner, N. "Z3: An Efficient SMT Solver." TACAS 2008. Springer.

   • Introduces Z3 solver with bitvector and theory reasoning; industry-standard for circuit verification.

3. Clarke, E. M., Grumberg, O., & Peled, D. A. Model Checking. MIT Press, 1999.

   • Classic text on formal verification; CSP/SMT techniques are fundamental to model-checking engines.

4. Cinelli, G., Chandra, R., & Bertossi, L. "A Survey of Algorithms for Constraint Satisfaction." ACM Comput. Surv. 48, 2015.

   • Covers constraint solving foundations and their application to hardware and protocol verification.

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