Skip to content
View gowrivlsi's full-sized avatar
🎯
Focusing
🎯
Focusing
  • VLSI 1st Institute
  • Bengaluru
  • 14:50 (UTC -12:00)
  • LinkedIn in/gowrish289

Block or report gowrivlsi

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
gowrivlsi/README.md

💫 About Me:

🔭Electronics & Communication Engineering student specializing in VLSI Design and Verification with strong interest in RTL Design and UVM-based verification.

Currently undergoing professional VLSI training at VLSI 1st, Bengaluru, gaining hands-on experience in Verilog, SystemVerilog, UVM, simulation, and digital design methodologies.

B.E. in Electronics & Communication Engineering (2021–2025) | CGPA: 8.14

Actively building and sharing projects related to RTL development, functional verification, and chip design. I’m currently working on
👯 I’m looking to collaborate on
🤝 I’m looking for help with
🌱 I’m currently learning
💬 Ask me about
⚡ Fun fact

🌐 Socials:

LinkedIn email

💻 Tech Stack:

C

📊 GitHub Stats:



🔝 Top Contributed Repo

Pinned Loading

  1. VERILOG_CODES VERILOG_CODES Public

    Verilog HDL practice repository containing combinational, sequential, and behavioural design examples developed during VLSI training, with testbenches, waveforms, and schematics.

    Verilog

  2. gowrivlsi gowrivlsi Public

    Electronics & Communication Engineering student specializing in VLSI Design & Verification with strong interest in RTL & UVM. Currently training at VLSI 1st, Bengaluru with hands-on experience in V…

  3. VERILOG_CODES_PROJECTS VERILOG_CODES_PROJECTS Public

    Collection of RTL and Verilog projects including FIFO designs, FSM systems, parameterized RAM, and PCIe SERDES implementation with testbenches, waveforms, and schematics.

    Verilog