Debug support request: Tinyusb with dwc2 does not work with .net application #3680

Jay20194 · 2026-06-05T19:14:43Z

Jay20194
Jun 5, 2026

Hey,
I am a USB newbie and need your support to debug my first project with USB.
After trying out a lot, I have no idea where to continue search the error and I would love to get some advises.

Project:
I have designed a microcontroller board with a STM32F105 and a PC application based on .net to change parameters on the board. Both use my own serial protocol to exchange information. The PC OS is Ubuntu and the micro uses FreeRTOS.
Previous versions of the microcontroller board used a uart with uart2usb converter to interact with the PC, but the same serial protocol and the same PC application without any problems.
The new version uses the STM32F105 with the dwc2 peripheral and a USB-C port on the board. And Tinyusb ;)
Within the PC .net application I am using "System.IO.Ports" as interface library, but due to known issues only the "Basetream" object of it.

Problem:
When I am connecting the board to the PC via USB, everything looks ok. Board is detected, enumeration works and the serial ports gets detected by ubunutu, no errors or warnings in dmesg.
But starting the .net application trying to connect via it, results in sending the 1. message and never getting a reply.
The micro receives the message and replies as expected, but the .net application never receives this reply.

This the debug output of tinyusb, while trying to send the serial commands: (device was already connected)

[2026-05-31T18:43:02.842Z, +787321ms] 
[2026-05-31T18:43:02.843Z, +787322ms] USBD Setup Received 21 22 03 00 00 00 00 00 
[2026-05-31T18:43:02.843Z, +787322ms]   CDC control request
[2026-05-31T18:43:02.843Z, +787322ms]   Queue EP 80 with 0 bytes ...
[2026-05-31T18:43:02.843Z, +787322ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-05-31T18:43:02.844Z, +787323ms]   Set Control Line State: DTR = 1, RTS = 1
[2026-05-31T18:43:02.844Z, +787323ms] 
[2026-05-31T18:43:02.844Z, +787323ms] USBD Setup Received 21 22 02 00 00 00 00 00 
[2026-05-31T18:43:02.844Z, +787323ms]   CDC control request
[2026-05-31T18:43:02.844Z, +787323ms]   Queue EP 80 with 0 bytes ...
[2026-05-31T18:43:02.845Z, +787324ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-05-31T18:43:02.845Z, +787324ms]   Set Control Line State: DTR = 0, RTS = 1
[2026-05-31T18:43:02.845Z, +787324ms] 
[2026-05-31T18:43:02.846Z, +787325ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-05-31T18:43:02.846Z, +787325ms]   CDC control request
[2026-05-31T18:43:02.846Z, +787325ms]   Queue EP 80 with 0 bytes ...
[2026-05-31T18:43:02.846Z, +787325ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-05-31T18:43:02.846Z, +787325ms]   Set Control Line State: DTR = 0, RTS = 0
[2026-05-31T18:43:02.865Z, +787343ms] USBD Xfer Complete on EP 02 with 3 bytes
[2026-05-31T18:43:02.865Z, +787343ms]   CDC xfer callback
[2026-05-31T18:43:07.876Z, +792355ms] 
[2026-05-31T18:43:07.876Z, +792355ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-05-31T18:43:07.876Z, +792355ms]   CDC control request
[2026-05-31T18:43:07.876Z, +792355ms]   Queue EP 80 with 0 bytes ...
[2026-05-31T18:43:07.876Z, +792355ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-05-31T18:43:07.876Z, +792355ms]   Set Control Line State: DTR = 0, RTS = 0`

Debugging attempts:
Next I tried several combinations of hardware and pc tools find the source of the error.

	microboard (dwc2)	F103_Bluepill (stm32_fsusb)	microboard_with_STMCube (dwc2)
Serial terminal	ok	ok
.net application	error	ok	ok

UsbInterface_Descriptors.cpp

change from my PC application to a serial terminal tool (VS Code Serial monitor extension)
With sending the same commands I get the expected reply without any issues. I attached the tinyusb debug output too:

[2026-05-31T18:41:36.072Z, +700551ms] 
[2026-05-31T18:41:36.073Z, +700552ms] USBD Setup Received 21 22 03 00 00 00 00 00 
[2026-05-31T18:41:36.073Z, +700552ms]   CDC control request
[2026-05-31T18:41:36.073Z, +700552ms]   Queue EP 80 with 0 bytes ...
[2026-05-31T18:41:36.073Z, +700552ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-05-31T18:41:36.073Z, +700552ms]   Set Control Line State: DTR = 1, RTS = 1
[2026-05-31T18:41:41.130Z, +705608ms] USBD Xfer Complete on EP 02 with 3 bytes
[2026-05-31T18:41:41.130Z, +705608ms]   CDC xfer callback
[2026-05-31T18:41:41.131Z, +705609ms]   Queue FIFO EP 02 with 64 bytes ... OK
[2026-05-31T18:41:41.131Z, +705609ms]   Queue FIFO EP 82 with 4 bytes ... OK
[2026-05-31T18:41:41.131Z, +705609ms] USBD Xfer Complete on EP 82 with 4 bytes
[2026-05-31T18:41:41.131Z, +705609ms]   CDC xfer callback
[2026-05-31T18:41:42.716Z, +707194ms] USBD Xfer Complete on EP 02 with 3 bytes
[2026-05-31T18:41:42.716Z, +707194ms]   CDC xfer callback
[2026-05-31T18:41:42.716Z, +707194ms]   Queue FIFO EP 02 with 64 bytes ... OK
[2026-05-31T18:41:42.717Z, +707195ms]   Queue FIFO EP 82 with 17 bytes ... OK
[2026-05-31T18:41:42.717Z, +707195ms] USBD Xfer Complete on EP 82 with 17 bytes
[2026-05-31T18:41:42.717Z, +707195ms]   CDC xfer callback
[2026-05-31T18:41:44.406Z, +708885ms] 
[2026-05-31T18:41:44.406Z, +708885ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-05-31T18:41:44.406Z, +708885ms]   CDC control request
[2026-05-31T18:41:44.406Z, +708885ms]   Queue EP 80 with 0 bytes ...
[2026-05-31T18:41:44.406Z, +708885ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-05-31T18:41:44.406Z, +708885ms]   Set Control Line State: DTR = 0, RTS = 0

using my pc application but a STM32F103 Bluepill board (STM_FSUSB device not dwc2)
The Bluepill ran the "cdc_msc_freertos" example and I added the needed reply from my serial protocol to the main function and everything works just fine...

[2026-06-05T17:29:23.620Z, +200048ms] 
[2026-06-05T17:29:23.622Z, +200051ms] USBD Setup Received 21 22 03 00 00 00 00 00 
[2026-06-05T17:29:23.622Z, +200051ms]   CDC control request
[2026-06-05T17:29:23.622Z, +200051ms]   Queue EP 80 with 0 bytes ...
[2026-06-05T17:29:23.622Z, +200051ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-05T17:29:23.622Z, +200051ms]   Set Control Line State: DTR = 1, RTS = 1
[2026-06-05T17:29:23.625Z, +200053ms] 
[2026-06-05T17:29:23.625Z, +200053ms] USBD Setup Received 21 22 02 00 00 00 00 00 
[2026-06-05T17:29:23.625Z, +200053ms]   CDC control request
[2026-06-05T17:29:23.625Z, +200053ms]   Queue EP 80 with 0 bytes ...
[2026-06-05T17:29:23.625Z, +200053ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-05T17:29:23.625Z, +200053ms]   Set Control Line State: DTR = 0, RTS = 1
[2026-06-05T17:29:23.625Z, +200053ms] 
[2026-06-05T17:29:23.625Z, +200053ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-06-05T17:29:23.625Z, +200053ms]   CDC control request
[2026-06-05T17:29:23.625Z, +200053ms]   Queue EP 80 with 0 bytes ...
[2026-06-05T17:29:23.626Z, +200055ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-05T17:29:23.626Z, +200055ms]   Set Control Line State: DTR = 0, RTS = 0
[2026-06-05T17:29:23.659Z, +200087ms] USBD Xfer Complete on EP 02 with 3 bytes
[2026-06-05T17:29:23.659Z, +200087ms]   CDC xfer callback
[2026-06-05T17:29:23.661Z, +200089ms]   Queue FIFO EP 02 with 64 bytes ... OK
[2026-06-05T17:29:23.661Z, +200089ms]   Queue FIFO EP 82 with 4 bytes ... OK
[2026-06-05T17:29:23.661Z, +200089ms] USBD Xfer Complete on EP 82 with 4 bytes
[2026-06-05T17:29:23.661Z, +200089ms]   CDC xfer callback
[2026-06-05T17:29:23.674Z, +200103ms] USBD Xfer Complete on EP 02 with 3 bytes
[2026-06-05T17:29:23.674Z, +200103ms]   CDC xfer callback
[2026-06-05T17:29:23.676Z, +200105ms]   Queue FIFO EP 02 with 64 bytes ... OK
[2026-06-05T17:29:23.676Z, +200105ms]   Queue FIFO EP 82 with 17 bytes ... OK
[2026-06-05T17:29:23.676Z, +200105ms] USBD Xfer Complete on EP 82 with 17 bytes
[2026-06-05T17:29:23.676Z, +200105ms]   CDC xfer callback
[2026-06-05T17:29:25.438Z, +201866ms] 
[2026-06-05T17:29:25.438Z, +201866ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-06-05T17:29:25.438Z, +201866ms]   CDC control request
[2026-06-05T17:29:25.438Z, +201866ms]   Queue EP 80 with 0 bytes ...
[2026-06-05T17:29:25.438Z, +201866ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-05T17:29:25.438Z, +201866ms]   Set Control Line State: DTR = 0, RTS = 0

using my pc application but and my microcontroller board but running a stm32Cube example with the stm32 usb library (dwc2)
I added the needed reply from my serial protocol to the main function and it works.
Sorry, I did not spent the time to figure out, how to get the debug log of the stm usb lib via RTT.

Last but not least I attached my USB desciptors file and my tinyusb config.
UsbInterface_Descriptors.cpp

I am not able to upload a ".h" file...

/*
 * The MIT License (MIT)
 *
 * Copyright (c) 2019 Ha Thach (tinyusb.org)
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#ifndef TUSB_CONFIG_H_
#define TUSB_CONFIG_H_

#ifdef __cplusplus
 extern "C" {
#endif

//--------------------------------------------------------------------+
// Board Specific Configuration
//--------------------------------------------------------------------+

// // RHPort number used for device can be defined by board.mk, default to port 0
#ifndef BOARD_TUD_RHPORT
#define BOARD_TUD_RHPORT     0
#endif

// // RHPort max operational speed can defined by board.mk
#ifndef BOARD_TUD_MAX_SPEED
#define BOARD_TUD_MAX_SPEED   OPT_MODE_FULL_SPEED
#endif

//--------------------------------------------------------------------
// COMMON CONFIGURATION
//--------------------------------------------------------------------

// defined by board.mk
#ifndef CFG_TUSB_MCU
#define CFG_TUSB_MCU OPT_MCU_STM32F1
#endif

// This examples use FreeRTOS
#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS           OPT_OS_FREERTOS
#endif

// can be defined by compiler in DEBUG build
#ifdef NDEBUG
#define CFG_TUSB_DEBUG        0
#else
#define CFG_TUSB_DEBUG        1
#endif

// Enable Device stack
#define CFG_TUD_ENABLED       1

// Default is max speed that hardware controller could support with on-chip PHY
#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED

/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
 * Tinyusb use follows macros to declare transferring memory so that they can be put
 * into those specific section.
 * e.g
 * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
 * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
 */
#ifndef CFG_TUSB_MEM_SECTION
#define CFG_TUSB_MEM_SECTION
#endif

#ifndef CFG_TUSB_MEM_ALIGN
#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
#endif

//--------------------------------------------------------------------
// DEVICE CONFIGURATION
//--------------------------------------------------------------------

#ifndef CFG_TUD_ENDPOINT0_SIZE
#define CFG_TUD_ENDPOINT0_SIZE   64
#endif

//------------- CLASS -------------//
#define CFG_TUD_CDC              1
#define CFG_TUD_MSC              0
#define CFG_TUD_HID              0
#define CFG_TUD_MIDI             0
#define CFG_TUD_VENDOR           0

#define CFG_TUD_CDC_NOTIFY        1 // Enable use of notification endpoint

// CDC FIFO size of TX and RX
#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 512)

// CDC Endpoint transfer buffer size, more is faster
// Leave it as default size (512 for HS, 64 for FS) unless your host application
// is able to send ZLP (Zero Length Packet) to terminate transfer !
#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)

#ifdef __cplusplus
 }
#endif

#endif /* TUSB_CONFIG_H_ */

HiFiPhile · 2026-06-05T19:35:58Z

HiFiPhile
Jun 5, 2026
Collaborator

Hi, from both log I see that device received the data:

[2026-05-31T18:43:02.865Z, +787343ms] USBD Xfer Complete on EP 02 with 3 bytes
[2026-05-31T18:43:02.865Z, +787343ms]   CDC xfer callback

But in the 1st log there is no data sending from the device, from 2nd log:

Queue FIFO EP 82 with 4 bytes ... OK

0 replies

Jay20194 · 2026-06-07T15:15:04Z

Jay20194
Jun 7, 2026
Author

Thanks for reply.
I double checked how the transfer is being performed in my faulty setup (STM32F105 + .net application).

.net application sends message (confirmed by log message after the transmit statement)
Wireshark logs the request message as sent to the micro + confirmation by the micro
Tinyusb on the micro logs the request message is received

Next step should be my FreeRTOS CDC task, that receives the message and processes it, but this does not happen.

If I open the port in a serial terminal afterwards, the CDC task in the micro fires without my sending a new message.

How can I debug this behaviour any further?

This is the task implementation. I am using FreeRTOS-Cpp which is a C++ wrapper for the standard FreeRTOS task including a task function.

void Tasks::UsbCdc::taskFunction()
{
  while (1) {
    if(tud_cdc_connected())
    {
      while (tud_cdc_available()) {
        auto& receiveBlock {Interface->GetReceiveBlock()};

        size_t readBytes = tud_cdc_read(&receiveBlock.GetFirstEmptyElement(), receiveBlock.size() - receiveBlock.GetUsedBytes());

        receiveBlock.ManipulateUsedBytes(static_cast<int>(readBytes));
      
      }
    }

    this->delay(1);
  }
}

Wireshark log (3.16 is my board):

1	0.000000	host	3.16.0	USB	64	GET DESCRIPTOR Request DEVICE
53	0.002864	3.16.0	host	USB	82	GET DESCRIPTOR Response DEVICE
54	0.002879	host	3.16.0	USB	64	GET DESCRIPTOR Request CONFIGURATION
135	0.004861	3.16.0	host	USB	73	GET DESCRIPTOR Response CONFIGURATION
136	0.004868	host	3.16.0	USB	64	GET DESCRIPTOR Request CONFIGURATION
281	0.007852	3.16.0	host	USB	139	GET DESCRIPTOR Response CONFIGURATION
200670	13.281773	host	3.16.1	USB	64	URB_INTERRUPT in
200671	13.281777	host	3.16.2	USB	64	URB_BULK in
200672	13.281780	host	3.16.2	USB	64	URB_BULK in
200673	13.281781	host	3.16.2	USB	64	URB_BULK in
200674	13.281783	host	3.16.2	USB	64	URB_BULK in
200675	13.281784	host	3.16.2	USB	64	URB_BULK in
200676	13.281786	host	3.16.2	USB	64	URB_BULK in
200677	13.281787	host	3.16.2	USB	64	URB_BULK in
200678	13.281788	host	3.16.2	USB	64	URB_BULK in
200679	13.281790	host	3.16.2	USB	64	URB_BULK in
200680	13.281791	host	3.16.2	USB	64	URB_BULK in
200681	13.281792	host	3.16.2	USB	64	URB_BULK in
200682	13.281793	host	3.16.2	USB	64	URB_BULK in
200683	13.281795	host	3.16.2	USB	64	URB_BULK in
200684	13.281796	host	3.16.2	USB	64	URB_BULK in
200685	13.281798	host	3.16.2	USB	64	URB_BULK in
200686	13.281799	host	3.16.2	USB	64	URB_BULK in
200688	13.281806	host	3.16.0	USBCOM	64	SET CONTROL LINE STATE Request
200697	13.282665	3.16.0	host	USB	64	URB_CONTROL out
200704	13.283189	host	3.16.0	USBCOM	64	SET CONTROL LINE STATE Request
200722	13.283857	3.16.0	host	USB	64	URB_CONTROL out
200739	13.284240	host	3.16.0	USBCOM	64	SET CONTROL LINE STATE Request
200767	13.284971	3.16.0	host	USB	64	URB_CONTROL out
201074	13.301245	host	3.16.2	USB	67	URB_BULK out
201075	13.301311	3.16.2	host	USB	64	URB_BULK out
215949	14.295741	host	3.16.0	USBCOM	64	SET CONTROL LINE STATE Request
215981	14.296633	3.16.0	host	USB	64	URB_CONTROL out
215982	14.296908	3.16.1	host	USB	64	URB_INTERRUPT in
215983	14.296974	3.16.2	host	USB	64	URB_BULK in
215984	14.297041	3.16.2	host	USB	64	URB_BULK in
215985	14.297108	3.16.2	host	USB	64	URB_BULK in
215986	14.297176	3.16.2	host	USB	64	URB_BULK in
215987	14.297243	3.16.2	host	USB	64	URB_BULK in
215988	14.297310	3.16.2	host	USB	64	URB_BULK in
215989	14.297378	3.16.2	host	USB	64	URB_BULK in
215990	14.297445	3.16.2	host	USB	64	URB_BULK in
215993	14.297511	3.16.2	host	USB	64	URB_BULK in
215995	14.297580	3.16.2	host	USB	64	URB_BULK in
216000	14.297681	3.16.2	host	USB	64	URB_BULK in
216005	14.297748	3.16.2	host	USB	64	URB_BULK in
216006	14.297815	3.16.2	host	USB	64	URB_BULK in
216007	14.297883	3.16.2	host	USB	64	URB_BULK in
216008	14.297950	3.16.2	host	USB	64	URB_BULK in
216009	14.298020	3.16.2	host	USB	64	URB_BULK in

Tinyusb log:


[2026-06-07T15:01:03.970Z, +000512ms] USBD init on controller 0, speed = Auto
[2026-06-07T15:01:03.970Z, +000512ms] sizeof(usbd_device_t) = 39
[2026-06-07T15:01:03.970Z, +000512ms] sizeof(dcd_event_t) = 12
[2026-06-07T15:01:03.970Z, +000512ms] sizeof(tu_fifo_t) = 20
[2026-06-07T15:01:03.970Z, +000512ms] sizeof(tu_edpt_stream_t) = 120
[2026-06-07T15:01:03.970Z, +000512ms] CDC init
[2026-06-07T15:01:03.970Z, +000512ms] guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
[2026-06-07T15:01:03.970Z, +000512ms] 0x00001000, 0x4F54272A, 0x00000000, 0x228DCD20, 0x020001E8, 0x0FF00030
[2026-06-07T15:01:03.970Z, +000512ms] Fullspeed PHY init
[2026-06-07T15:01:03.970Z, +000512ms] DMA = 0
[2026-06-07T15:01:03.970Z, +000512ms] USBD Bus Reset : Full Speed
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 80 06 00 01 00 00 40 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Get Descriptor Device
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 80 with 18 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 18 bytes
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:03.970Z, +000512ms] USBD Bus Reset : Full Speed
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 00 05 04 00 00 00 00 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Set Address
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 80 06 00 01 00 00 12 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Get Descriptor Device
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 80 with 18 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 18 bytes
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 80 06 00 02 00 00 4B 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Get Descriptor Configuration[0]
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 80 with 64 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 64 bytes
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 80 with 11 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 11 bytes
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 80 06 03 03 09 04 FF 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Get Descriptor String[3]
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 80 with 20 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 20 bytes
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 00 09 01 00 00 00 00 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Set Configuration
[2026-06-07T15:01:03.970Z, +000512ms]   Open EP 81 with Size = 16
[2026-06-07T15:01:03.970Z, +000512ms]   Open EP 02 with Size = 64
[2026-06-07T15:01:03.970Z, +000512ms]   Queue FIFO EP 02 with 64 bytes ... OK
[2026-06-07T15:01:03.970Z, +000512ms]   Open EP 82 with Size = 64
[2026-06-07T15:01:03.970Z, +000512ms]   CDC opened
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 80 with 0 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 80 00 00 00 00 00 02 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Get Status
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 80 with 2 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 80 with 2 bytes
[2026-06-07T15:01:03.970Z, +000512ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:03.970Z, +000512ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] USBD Setup Received 80 06 00 01 00 00 12 00 
[2026-06-07T15:01:03.970Z, +000512ms]   Get Descriptor Device
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:03.970Z, +000512ms] 
[2026-06-07T15:01:32.886Z, +029428ms] 
[2026-06-07T15:01:32.886Z, +029428ms] USBD Setup Received 80 06 00 01 00 00 12 00 
[2026-06-07T15:01:32.886Z, +029428ms]   Get Descriptor Device
[2026-06-07T15:01:32.886Z, +029428ms]   Queue EP 80 with 18 bytes ...
[2026-06-07T15:01:32.886Z, +029428ms] USBD Xfer Complete on EP 80 with 18 bytes
[2026-06-07T15:01:32.887Z, +029429ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:32.887Z, +029429ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:32.887Z, +029429ms] 
[2026-06-07T15:01:32.888Z, +029430ms] USBD Setup Received 80 06 00 02 00 00 09 00 
[2026-06-07T15:01:32.888Z, +029430ms]   Get Descriptor Configuration[0]
[2026-06-07T15:01:32.888Z, +029430ms]   Queue EP 80 with 9 bytes ...
[2026-06-07T15:01:32.888Z, +029430ms] USBD Xfer Complete on EP 80 with 9 bytes
[2026-06-07T15:01:32.889Z, +029431ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:32.889Z, +029431ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:32.891Z, +029432ms] 
[2026-06-07T15:01:32.891Z, +029432ms] USBD Setup Received 80 06 00 02 00 00 4B 00 
[2026-06-07T15:01:32.892Z, +029434ms]   Get Descriptor Configuration[0]
[2026-06-07T15:01:32.892Z, +029434ms]   Queue EP 80 with 64 bytes ...
[2026-06-07T15:01:32.892Z, +029434ms] USBD Xfer Complete on EP 80 with 64 bytes
[2026-06-07T15:01:32.892Z, +029434ms]   Queue EP 80 with 11 bytes ...
[2026-06-07T15:01:32.892Z, +029434ms] USBD Xfer Complete on EP 80 with 11 bytes
[2026-06-07T15:01:32.893Z, +029435ms]   Queue EP 00 with 0 bytes ...
[2026-06-07T15:01:32.893Z, +029435ms] USBD Xfer Complete on EP 00 with 0 bytes
[2026-06-07T15:01:46.167Z, +042709ms] 
[2026-06-07T15:01:46.167Z, +042709ms] USBD Setup Received 21 22 03 00 00 00 00 00 
[2026-06-07T15:01:46.167Z, +042709ms]   CDC control request
[2026-06-07T15:01:46.167Z, +042709ms]   Queue EP 80 with 0 bytes ...
[2026-06-07T15:01:46.167Z, +042709ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:01:46.167Z, +042709ms]   Set Control Line State: DTR = 1, RTS = 1
[2026-06-07T15:01:46.168Z, +042710ms] 
[2026-06-07T15:01:46.168Z, +042710ms] USBD Setup Received 21 22 02 00 00 00 00 00 
[2026-06-07T15:01:46.168Z, +042710ms]   CDC control request
[2026-06-07T15:01:46.168Z, +042710ms]   Queue EP 80 with 0 bytes ...
[2026-06-07T15:01:46.168Z, +042710ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:01:46.169Z, +042711ms]   Set Control Line State: DTR = 0, RTS = 1
[2026-06-07T15:01:46.169Z, +042711ms] 
[2026-06-07T15:01:46.169Z, +042711ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-06-07T15:01:46.169Z, +042711ms]   CDC control request
[2026-06-07T15:01:46.169Z, +042711ms]   Queue EP 80 with 0 bytes ...
[2026-06-07T15:01:46.171Z, +042713ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:01:46.171Z, +042713ms]   Set Control Line State: DTR = 0, RTS = 0
[2026-06-07T15:01:46.186Z, +042728ms] USBD Xfer Complete on EP 02 with 3 bytes
[2026-06-07T15:01:46.186Z, +042728ms]   CDC xfer callback
[2026-06-07T15:01:47.179Z, +043721ms] 
[2026-06-07T15:01:47.182Z, +043724ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-06-07T15:01:47.182Z, +043724ms]   CDC control request
[2026-06-07T15:01:47.182Z, +043724ms]   Queue EP 80 with 0 bytes ...
[2026-06-07T15:01:47.182Z, +043724ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:01:47.182Z, +043724ms]   Set Control Line State: DTR = 0, RTS = 0
RTT:0>

These are the logs, if I open the port in a serial terminal afterwards:
Wireshark:

1	0.000000	host	3.16.0	USB	64	GET DESCRIPTOR Request DEVICE
57	0.001656	3.16.0	host	USB	82	GET DESCRIPTOR Response DEVICE
58	0.001667	host	3.16.0	USB	64	GET DESCRIPTOR Request CONFIGURATION
131	0.003556	3.16.0	host	USB	73	GET DESCRIPTOR Response CONFIGURATION
133	0.003567	host	3.16.0	USB	64	GET DESCRIPTOR Request CONFIGURATION
216	0.005522	3.16.0	host	USB	139	GET DESCRIPTOR Response CONFIGURATION
324767	21.667955	host	3.16.1	USB	64	URB_INTERRUPT in
324768	21.667967	host	3.16.2	USB	64	URB_BULK in
324769	21.667969	host	3.16.2	USB	64	URB_BULK in
324770	21.667971	host	3.16.2	USB	64	URB_BULK in
324771	21.667973	host	3.16.2	USB	64	URB_BULK in
324772	21.667975	host	3.16.2	USB	64	URB_BULK in
324773	21.667976	host	3.16.2	USB	64	URB_BULK in
324774	21.667979	host	3.16.2	USB	64	URB_BULK in
324775	21.667981	host	3.16.2	USB	64	URB_BULK in
324776	21.667983	host	3.16.2	USB	64	URB_BULK in
324777	21.667985	host	3.16.2	USB	64	URB_BULK in
324778	21.667986	host	3.16.2	USB	64	URB_BULK in
324779	21.667988	host	3.16.2	USB	64	URB_BULK in
324780	21.667990	host	3.16.2	USB	64	URB_BULK in
324781	21.667992	host	3.16.2	USB	64	URB_BULK in
324782	21.667993	host	3.16.2	USB	64	URB_BULK in
324783	21.667995	host	3.16.2	USB	64	URB_BULK in
324784	21.668000	host	3.16.0	USBCOM	64	SET CONTROL LINE STATE Request
324795	21.668721	3.16.0	host	USB	64	URB_CONTROL out
324829	21.669704	3.16.2	host	USB	68	URB_BULK in
324830	21.669709	host	3.16.2	USB	64	URB_BULK in
572768	38.309234	host	3.16.0	USBCOM	64	SET CONTROL LINE STATE Request
572769	38.309715	3.16.0	host	USB	64	URB_CONTROL out
572773	38.309875	3.16.1	host	USB	64	URB_INTERRUPT in
572777	38.309916	3.16.2	host	USB	64	URB_BULK in
572783	38.310029	3.16.2	host	USB	64	URB_BULK in
572788	38.310131	3.16.2	host	USB	64	URB_BULK in
572793	38.310204	3.16.2	host	USB	64	URB_BULK in
572798	38.310303	3.16.2	host	USB	64	URB_BULK in
572803	38.310375	3.16.2	host	USB	64	URB_BULK in
572804	38.310442	3.16.2	host	USB	64	URB_BULK in
572805	38.310524	3.16.2	host	USB	64	URB_BULK in
572812	38.310638	3.16.2	host	USB	64	URB_BULK in
572818	38.310733	3.16.2	host	USB	64	URB_BULK in
572821	38.310835	3.16.2	host	USB	64	URB_BULK in
572825	38.310915	3.16.2	host	USB	64	URB_BULK in
572827	38.311001	3.16.2	host	USB	64	URB_BULK in
572832	38.311107	3.16.2	host	USB	64	URB_BULK in
572836	38.311214	3.16.2	host	USB	64	URB_BULK in
572837	38.311285	3.16.2	host	USB	64	URB_BULK in

Tinyusb:

[2026-06-07T15:10:56.881Z, +593423ms] 
[2026-06-07T15:10:56.881Z, +593423ms] USBD Setup Received 21 22 03 00 00 00 00 00 
[2026-06-07T15:10:56.881Z, +593423ms]   CDC control request
[2026-06-07T15:10:56.881Z, +593423ms]   Queue EP 80 with 0 bytes ...
[2026-06-07T15:10:56.883Z, +593425ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:10:56.883Z, +593425ms]   Set Control Line State: DTR = 1, RTS = 1
[2026-06-07T15:10:56.883Z, +593425ms]   Queue FIFO EP 02 with 64 bytes ... OK
[2026-06-07T15:10:56.883Z, +593425ms] Received: 3
[2026-06-07T15:10:56.883Z, +593425ms] Sent: ProtVer
[2026-06-07T15:10:56.883Z, +593425ms]   Queue FIFO EP 82 with 4 bytes ... OK
[2026-06-07T15:10:56.884Z, +593426ms] USBD Xfer Complete on EP 82 with 4 bytes
[2026-06-07T15:10:56.884Z, +593426ms]   CDC xfer callback
[2026-06-07T15:11:13.522Z, +610064ms] 
[2026-06-07T15:11:13.522Z, +610064ms] USBD Setup Received 21 22 00 00 00 00 00 00 
[2026-06-07T15:11:13.522Z, +610064ms]   CDC control request
[2026-06-07T15:11:13.522Z, +610064ms]   Queue EP 80 with 0 bytes ...
[2026-06-07T15:11:13.524Z, +610066ms] USBD Xfer Complete on EP 80 with 0 bytes
[2026-06-07T15:11:13.524Z, +610066ms]   Set Control Line State: DTR = 0, RTS = 0
RTT:0>

0 replies

Jay20194 · 2026-06-16T19:05:54Z

Jay20194
Jun 16, 2026
Author

Could anyone help me out with my problem?

I do not know what I am doing wrong and I do not want to open a bug ticket, but I do not know how to help myself.

1 reply

HiFiPhile Jun 16, 2026
Collaborator

I suppose you have some embedded development experience, otherwise why using a CPP framework that nearly nobody used ?

auto& receiveBlock {Interface->GetReceiveBlock()};
size_t readBytes = tud_cdc_read(&receiveBlock.GetFirstEmptyElement(), receiveBlock.size() - receiveBlock.GetUsedBytes());
receiveBlock.ManipulateUsedBytes(static_cast(readBytes));

How can anyone give you help without knowing what's behind these CPP code ?

Navigation Menu

Uh oh!

Debug support request: Tinyusb with dwc2 does not work with .net application #3680

Uh oh!

{{title}}

Uh oh!

Uh oh!

{{editor}}'s edit

{{editor}}'s edit

Uh oh!

Replies: 3 comments 1 reply

Uh oh!

{{title}}

Uh oh!

Uh oh!

{{title}}

Uh oh!

Uh oh!

{{title}}

Uh oh!

Uh oh!

{{title}}

Uh oh!

Select a reply

Uh oh!

Uh oh!

Debug support request: Tinyusb with dwc2 does not work with .net application #3680

Uh oh!

Uh oh!

Jay20194 Jun 5, 2026

Replies: 3 comments · 1 reply

Uh oh!

HiFiPhile Jun 5, 2026 Collaborator

Uh oh!

Jay20194 Jun 7, 2026 Author

Uh oh!

Jay20194 Jun 16, 2026 Author

Uh oh!

HiFiPhile Jun 16, 2026 Collaborator

Jay20194
Jun 5, 2026

Replies: 3 comments 1 reply

HiFiPhile
Jun 5, 2026
Collaborator

Jay20194
Jun 7, 2026
Author

Jay20194
Jun 16, 2026
Author

HiFiPhile Jun 16, 2026
Collaborator