Fix ch32v103 hardfault & Add CH32V103C8T6 Bluepill board

[UMRnInside]

compile but does not run (no blinky), probably due to compile/linker/startup issue

#2674 has a startup issue in board_init() : __disable_irq() from CH32V103 EVT calls csrc mstatus, 0x88 in U-mode (which is only allowed in M-mode)

https://github.com/openwch/ch32v103/blob/f99a84c4c42b6fb676560a9b8b7c737401efe0ad/EVT/EXAM/SRC/Core/core_riscv.h#L144-L155

__disable_irq() in CH32V307 EVT (probably also in CH32V203), however, uses vendor-defined CSR 0x800. This CSR is writable in U-mode, according to QingKeV3 Processor Manual:

https://github.com/openwch/ch32v307/blob/7e33c66cd91008054d2a37db534b10162d1f0c6e/EVT/EXAM/SRC/Core/core_riscv.h#L141-L145

Now you can see the LED blinking, log outputting from UART(if LOG=2), but cdc_msc example is still not working.

USBD init on controller 0, speed = Auto
sizeof(usbd_device_t) = 55
sizeof(dcd_event_t) = 12
sizeof(tu_fifo_t) = 12
sizeof(tu_edpt_stream_t) = 24
CDC init
MSC init
sizeof(mscd_interface_t) = 64
USBD Bus Reset : Full Speed

USBD Setup Received 80 06 00 01 00 00 40 00 
  Get Descriptor Device
  Queue EP 80 with 18 bytes ...
USBD Xfer Complete on EP 80 with 18 bytes
  Queue EP 00 with 0 bytes ...

USBD Setup Received 80 06 00 01 00 00 40 00 
  Get Descriptor Device
  Queue EP 80 with 18 bytes ...
USBD Xfer Complete on EP 80 with 18 bytes
  Queue EP 00 with 0 bytes ...

[Copilot]

Pull request overview

This PR targets the CH32V103 BSP startup/hardfault issue by avoiding the vendor __disable_irq()/__enable_irq() implementation that traps when executed in U-mode, and it adds a new CH32V103C8T6 “Bluepill” board definition with appropriate flash/RAM linker sizing.

Changes:

• Avoids calling __disable_irq() / __enable_irq() in hw/bsp/ch32v10x/family.c to prevent hardfaults on CH32V103 EVT when running in U-mode.
• Adds a new ch32v103c_bluepill board (pins + build/linker settings).
• Enables CFG_EXAMPLE_MSC_DUAL_READONLY for the new board (matching the existing CH32V103R board setup).

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 2 comments.

File	Description
hw/bsp/ch32v10x/family.c	Skips global IRQ disable/enable in board_init() to avoid U-mode hardfault.
hw/bsp/ch32v10x/boards/ch32v103c_bluepill/board.mk	Sets CFG_EXAMPLE_MSC_DUAL_READONLY and defines flash/RAM sizes for the linker.
hw/bsp/ch32v10x/boards/ch32v103c_bluepill/board.h	Adds LED/button pin mappings and board metadata for the Bluepill variant.
hw/bsp/ch32v10x/boards/ch32v103c_bluepill/board.cmake	Mirrors board.mk settings for CMake builds (flash/RAM + compile definitions).

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[HiFiPhile]

Thank you, I've just fixed some CH32's DCD reliability issue, could you test again ?

[UMRnInside]

Tested, I got device descriptor read error -110.
I tested cdc_msc example on CH32V103C8T6 with latest commit (7b9f6ea) and fix-ch32v103-hardfault merged (locally).

MCU output with LOG=2:

USBD init on controller 0, speed = Auto
sizeof(usbd_device_t) = 76
sizeof(dcd_event_t) = 12
sizeof(tu_fifo_t) = 12
sizeof(tu_edpt_stream_t) = 24
CDC init
MSC init
sizeof(mscd_interface_t) = 64
USBD Bus Reset : Full Speed

USBD Setup Received 80 06 00 01 00 00 40 00 
  Get Descriptor Device
  Queue EP 80 with 18 bytes ...
USBD Xfer Complete on EP 80 with 18 bytes
  Queue EP 00 with 0 bytes ...

USBD Setup Received 80 06 00 01 00 00 40 00 
  Get Descriptor Device
  Queue EP 80 with 18 bytes ...
USBD Xfer Complete on EP 80 with 18 bytes
  Queue EP 00 with 0 bytes ...

And dmesg:

[ 3527.578511] usb 1-1.4: new full-speed USB device number 12 using xhci_hcd
[ 3542.926520] usb 1-1.4: device descriptor read/64, error -110

[HiFiPhile]

Thank you, just took a look and V103 has a different register layout:

V103:

V2x: