GitHub - hereisjayant/Simple-RISC-Machine-3-Memory-IO: Adding Memory and I/O to the “Simple RISC Machine”

Name		Name	Last commit message	Last commit date
Latest commit History 21 Commits
assembler		assembler
db		db
incremental_db		incremental_db
output_files		output_files
work		work
DE1_SoC.qsf		DE1_SoC.qsf
LDR, STR details.txt		LDR, STR details.txt
alu.v		alu.v
c5_pin_model_dump.txt		c5_pin_model_dump.txt
cpu.v		cpu.v
cygwinlab7.pdf		cygwinlab7.pdf
data.txt		data.txt
data_1.txt		data_1.txt
data_2.txt		data_2.txt
datapath.v		datapath.v
fsm.v		fsm.v
fsm_tb.v		fsm_tb.v
instructionDecoder.v		instructionDecoder.v
lab7.cr.mti		lab7.cr.mti
lab7.mpf		lab7.mpf
lab7.pdf		lab7.pdf
lab7.qpf		lab7.qpf
lab7_autograder_check.v		lab7_autograder_check.v
lab7_top.qsf		lab7_top.qsf
lab7_top.qsf.bak		lab7_top.qsf.bak
lab7_top.qws		lab7_top.qws
lab7_top.v		lab7_top.v
lex.yy.c		lex.yy.c
ram.v		ram.v
regfile.v		regfile.v
sas.zip		sas.zip
shifter.v		shifter.v
stage2.lst		stage2.lst
stage2.s		stage2.s
stage2.txt		stage2.txt
stage2_tb.v		stage2_tb.v
stage3.lst		stage3.lst
stage3.s		stage3.s
stage3.txt		stage3.txt
transcript		transcript
vsim.wlf		vsim.wlf