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feat: add configurable scratch region base GPA #1271
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2f3efed
feat: add configurable scratch region base GPA
danbugs 61b5aed
fix: make snapshot region writable for non-init-paging guests
danbugs b961eb1
fix: use init-paging feature gate for scratch GVA computation
danbugs 4b579d3
fix: use scratch base GPA instead of scratch size in page table walker
danbugs f5e6116
fix: initialize all segment registers and XSAVE state for MSHV/WHP co…
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -106,34 +106,55 @@ impl CommonSpecialRegisters { | |
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| #[cfg(not(feature = "init-paging"))] | ||
| pub(crate) fn standard_real_mode_defaults() -> Self { | ||
| // In real mode, all data/code segment registers must have valid | ||
| // limit, present, type_, and s fields. MSHV (unlike KVM) rejects | ||
| // the vCPU state if any segment has limit=0 / present=0. | ||
| let data_seg = CommonSegmentRegister { | ||
| base: 0, | ||
| selector: 0, | ||
| limit: 0xFFFF, | ||
| type_: 3, // data, read/write, accessed | ||
| present: 1, | ||
| s: 1, // non-system | ||
| ..Default::default() | ||
| }; | ||
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| CommonSpecialRegisters { | ||
| cs: CommonSegmentRegister { | ||
| base: 0, | ||
| selector: 0, | ||
| limit: 0xFFFF, | ||
| type_: 11, | ||
| type_: 11, // code, readable, accessed | ||
| present: 1, | ||
| s: 1, | ||
| s: 1, // non-system | ||
| ..Default::default() | ||
| }, | ||
| ds: CommonSegmentRegister { | ||
| ds: data_seg, | ||
| es: data_seg, | ||
| ss: data_seg, | ||
| fs: data_seg, | ||
| gs: data_seg, | ||
| tr: CommonSegmentRegister { | ||
| base: 0, | ||
| selector: 0, | ||
| limit: 0xFFFF, | ||
| type_: 3, | ||
| type_: 11, // 32-bit busy TSS | ||
| present: 1, | ||
| s: 1, | ||
| s: 0, // system segment | ||
| ..Default::default() | ||
| }, | ||
| tr: CommonSegmentRegister { | ||
| ldt: CommonSegmentRegister { | ||
| base: 0, | ||
| selector: 0, | ||
| limit: 0xFFFF, | ||
| type_: 11, | ||
| type_: 2, // LDT descriptor | ||
| present: 1, | ||
| s: 0, | ||
| s: 0, // system segment | ||
| ..Default::default() | ||
| }, | ||
| // CR0.ET (bit 4) is hardwired to 1 on modern x86 CPUs. | ||
| // MSHV rejects the vCPU state if ET is not set. | ||
|
Contributor
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. How hasn't mshv failed so far? was this scenario not tested before?
Member
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I don't believe there are many tests for the 16/32-bit guests. |
||
| cr0: 1 << 4, | ||
| ..Default::default() | ||
| } | ||
| } | ||
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I'm curious how this worked before
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It looks like at issue here is the difference between bringing up the vcpu in real vs long mode. Does the xsave reset call need to be there in both, or should it just be in real mode? I know we had tests of the long mode mshv stuff passing before.
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I think the real vs long is the issue here. When I did some investigation in mxcsr on kvm awhile back it did work fine in long mode.
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I agree that if we don't need this for some targets it would be nice to not waste cycles here