i2c: fine tune register values to meet the 100 kHz frequency requirement#78
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ddeshat merged 1 commit intointel:mainfrom Apr 17, 2026
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i2c: fine tune register values to meet the 100 kHz frequency requirement#78ddeshat merged 1 commit intointel:mainfrom
ddeshat merged 1 commit intointel:mainfrom
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The patch looks well and should be able to address the 100KHZ issue. |
kwd-doodling
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When ISH I2C is configured to standard frequency 100kHz and measured on different WCL RVP and customer reference designs the measured frequency reported is more than 101kHz The default values of the I2C_SS_SCL_HIGH REG values is increased by 140 to finetune clock frequency to 99.79kHz. This helps generate frequency less than 100kHz by default. Based on the WCL boards RVP below are the details on the I2C SCL Clock pulse tr(raise time)=189.6ns tf(fall time)=48.92ns tHIGH=4.7usec and tLOW=5.124usec. Frequency measured is 99.79kHz Signed-off-by: Deshatty, Deepti <deepti.deshatty@intel.com>
kwd-doodling
approved these changes
Apr 17, 2026
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i2c: fine tune register values to meet the 100 kHz frequency requirement
When ISH I2C is configured to standard frequency 100kHz and measured on different WCL RVP and customer reference designs the measured frequency reported is more than 101kHz
The default values of the I2C_SS_SCL_HIGH REG values is increased by 140 to finetune clock frequency to 99.79kHz. This helps generate frequency less than 100kHz by default.
Based on the WCL boards RVP below are the details on the I2C SCL Clock pulse
tr(raise time)=189.6ns tf(fall time)=48.92ns tHIGH=4.7usec and tLOW=5.124usec. Frequency measured is 99.79kHz
Captures attached:
