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[SYCL][NATIVECPU] Update Native CPU attributes test #15451

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Merged
merged 3 commits into from
Sep 30, 2024
Merged

[SYCL][NATIVECPU] Update Native CPU attributes test #15451

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b69d765
Update Native CPU attributes test
PietroGhg Sep 18, 2024
5f529b7
CHECK-NOT for work group barrier
PietroGhg Sep 19, 2024
85bfc2c
Add comment and fix check directive
PietroGhg Sep 19, 2024
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16 changes: 9 additions & 7 deletions sycl/test/check_device_code/native_cpu/native_cpu_attrs.cpp
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Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
// REQUIRES: native_cpu_ock
// RUN: %clangxx -fsycl -fsycl-targets=native_cpu -Xclang -sycl-std=2020 -mllvm -sycl-native-dump-device-ir %s | FileCheck %s
// RUN: %clangxx -fsycl -fsycl-targets=native_cpu -Xclang -sycl-std=2020 -mllvm -sycl-native-dump-device-ir %s &> %t.ll
// RUN: FileCheck %s --input-file %t.ll --check-prefix=CHECK-WG-BARRIER
// RUN: FileCheck %s --input-file %t.ll

#include "sycl.hpp"
using namespace sycl;
Expand All @@ -11,17 +13,17 @@ int main() {
deviceQueue.submit([&](handler &h) {
h.parallel_for<Test>(
r, [=](nd_item<2> it) {
it.barrier(access::fence_space::local_space);
//CHECK-DAG: call void @__mux_work_group_barrier({{.*}})
atomic_fence(memory_order::acquire, memory_scope::work_group);
//CHECK-DAG: call void @__mux_mem_barrier({{.*}})
});
});

}

//CHECK-DAG: define{{.*}}@__mux_work_group_barrier{{.*}}#[[ATTR:[0-9]+]]
//CHECK-DAG: [[ATTR]]{{.*}}convergent
// Currently Native CPU uses the WorkItemLoops pass from the oneAPI
// Construction Kit to materialize barriers, so the builtin shouldn't
// be referenced anymore in the module.
// CHECK-WG-BARRIER-NOT: @__mux_work_group_barrier

//CHECK-DAG: define{{.*}}@__mux_mem_barrier{{.*}}#[[ATTR_MEM:[0-9]+]]
//CHECK-DAG: [[ATTR_MEM]]{{.*}}convergent
// CHECK-DAG: define{{.*}}@__mux_mem_barrier{{.*}}#[[ATTR_MEM:[0-9]+]]
// CHECK-DAG: [[ATTR_MEM]]{{.*}}convergent
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