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[Doc] Add support for WCL in joint matrix #20795

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Dec 2, 2025
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[Doc] Add support for WCL in joint matrix #20795

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44 changes: 29 additions & 15 deletions sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc
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Original file line number Diff line number Diff line change
Expand Up @@ -1110,7 +1110,8 @@ This is currently available in devices with the architecture
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_dg2_g10`, `architecture::intel_gpu_dg2_g11`,
`architecture::intel_gpu_dg2_g12`, `architecture::intel_gpu_arl_h`,
`architecture::intel_gpu_ptl_h`, and `architecture::intel_gpu_ptl_u`.
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
and `architecture::intel_gpu_wcl`.

[frame="none",options="header"]
|======================
Expand All @@ -1119,39 +1120,44 @@ This is currently available in devices with the architecture
`matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32
|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
|8|`architecture::intel_gpu_dg2_g10,
architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
`architecture::intel_gpu_arl_h`
.2+| `matrix_type::uint8` .2+| `matrix_type::sint8` .2+|
`matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
|8|`architecture::intel_gpu_dg2_g10,
architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
`architecture::intel_gpu_arl_h`
.2+| `matrix_type::sint8` .2+| `matrix_type::uint8` .2+|
`matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
|8|`architecture::intel_gpu_dg2_g10,
architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
`architecture::intel_gpu_arl_h`
.2+| `matrix_type::sint8` .2+| `matrix_type::sint8` .2+|
`matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
|8|`architecture::intel_gpu_dg2_g10,
architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
`architecture::intel_gpu_arl_h`
.8+|`matrix_type::fp16` .8+| `matrix_type::fp16` .8+|
`matrix_type::fp32` .8+|`matrix_type::fp32` .1+| 16 .1+| 16 | 16
.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
.2+| 1 .2+| 64 | 16 |32
.2+| 32 .2+| 64 | 16 |32
.2+| +<=+ 8 | 16 .2+| 16
Expand All @@ -1163,27 +1169,31 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
`matrix_type::fp16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16
.6+| `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
.2+| 32 .2+| 64 | 16 | 32
.6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+|
`matrix_type::fp32` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16
.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
.2+| 32 .2+| 64 |16 | 32
.6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+|
`matrix_type::fp16` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16
.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 |32 .2+| 32 .2+| 64 | 16 | 32
.8+| `matrix_type::bf16` .8+| `matrix_type::bf16` .8+|
`matrix_type::fp32` .8+| `matrix_type::fp32` | 16 | 16 | 16
.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
.2+| 1 .2+| 64 | 16 | 32
.2+| 32 .2+| 64 | 16 |32
.2+| +<=+ 8 | 16 .2+| 16
Expand All @@ -1195,34 +1205,38 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
`matrix_type::bf16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16 .6+|
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
.2+| 32 .2+| 64 |16 | 32
.6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
`matrix_type::fp32` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+|
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
.2+| 32 .2+| 64 |16 | 32
.6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
`matrix_type::bf16` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+|
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
.2+| 32 .2+| 64 |16 | 32
| `matrix_type::tf32` | `matrix_type::tf32` |
`matrix_type::fp32` .2+| `matrix_type::fp32` | +<=+ 8 | 16 | 8 |
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
`architecture::intel_gpu_wcl`
|======================

===== Restrictions on `architecture::intel_gpu_pvc`,
`architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`,
`architecture::intel_gpu_lnl_m`, `architecture::intel_gpu_ptl_h`,
and `architecture::intel_gpu_ptl_u`
`architecture::intel_gpu_ptl_u`, and `architecture::intel_gpu_wcl`

- The `stride` parameter to `joint_matrix_load` and
`joint_matrix_store` has the following restrictions:
Expand Down