[libspirv] Align subgroup builtins and generic wrappers with downstream#21437
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uditagarwal97 merged 5 commits intointel:syclfrom Mar 17, 2026
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Changes * use __ATOMIC_SEQ_CST for SequentiallyConsistent semantics mapping. * add GroupOperation::ClusteredReduce and the non-uniform overload without ClusterSize. * route __spirv_BuiltInSubgroupSize through __clc_get_sub_group_size. * delete amdgcn-amdhsa/workitem/get_sub_group_size.cl which is the same as the generic get_sub_group_size.cl. * clang-format include order. llvm-diff shows no change to nvptx64-nvidia-cuda/libspirv.bc.
…v_AtomicFlagTestAndSet"" This reverts commit f74832c.
bratpiorka
approved these changes
Mar 10, 2026
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@intel/llvm-gatekeepers please consider merging |
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@intel/llvm-gatekeepers please consider merging |
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@intel/llvm-gatekeepers please consider merging |
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@intel/llvm-gatekeepers please merge, thanks |
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Changes
llvm-diff shows that only __spirv_AtomicFlagClear and __spirv_AtomicFlagTestAndSet
changed in nvptx64-nvidia-cuda/libspirv.bc, with lowering switched from
llvm.nvvm.atomic.exch to atomicrmw xchg. To preserve previous behavior,
we should override __clc_atomic_flag_clear and __clc_atomic_flag_test_and_set
for NVPTX; this is left for future work.