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[SYCL] PR 6 - Remove FPGA Attributes from SYCL FE#21785

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sarnex merged 3 commits intointel:syclfrom
premanandrao:remote_fpga_pr6
Apr 21, 2026
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[SYCL] PR 6 - Remove FPGA Attributes from SYCL FE#21785
sarnex merged 3 commits intointel:syclfrom
premanandrao:remote_fpga_pr6

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@premanandrao
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This removes the following attributes:

[[intel::loop_coalesce]]
[[intel::max_interleaving]]
[[intel::scheduler_target_fmax_mhz]]
[[intel::use_stall_enable_clusters]]

@premanandrao premanandrao requested a review from a team as a code owner April 15, 2026 18:08
@premanandrao premanandrao marked this pull request as draft April 15, 2026 18:09
@premanandrao premanandrao marked this pull request as ready for review April 15, 2026 20:04
@premanandrao
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@intel/llvm-gatekeepers, any ideas about this failure in SYCL Pre Commit on Linux?

error: variable 'eventRetains' set but not used [-Werror,-Wunused-but-set-global]
8 | static size_t eventRetains = 0;
| ^

The failure is in a unittest mock_opencl/mock_opencl.cpp, but the code that is being flagged has been there for nearly a year. Did the diagnostic severity change recently?

@sarnex
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sarnex commented Apr 20, 2026

Not sure why it started failing now but a PR is open to fix it here #21814

@premanandrao
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Not sure why it started failing now but a PR is open to fix it here #21814

Thank you!

@KornevNikita
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@premanandrao is this ready?

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@premanandrao is this ready?

Yes, the Jenkins failure seems unrelated.

@sarnex sarnex merged commit 3ee6128 into intel:sycl Apr 21, 2026
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4 participants