[SYCL][ESIMD] Limit allowed argument types for rol/ror functions #6569
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| __ESIMD_NS::simd<T0, SZ>> | ||
| rol(__ESIMD_NS::simd<T1, SZ> src0, __ESIMD_NS::simd<T1, SZ> src1) { | ||
| __ESIMD_API std::enable_if_t< | ||
| __ESIMD_NS::detail::is_type<T0, int16_t, uint16_t, int32_t, uint32_t>() && |
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This code needs more corrections to follow the restrictions in HW instructions.
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int64 vectors are allowed for PVC+
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it is not obvious from GenX-Intrinsics and bSPEC, but the HW instruction expects same bit-width for destination and source. If so, we could pass only 1 type to __esimd_rol
Potentially, instead of generating __esimd_rol we could generate SPIRV instruction rotate from this extended inst set: https://registry.khronos.org/SPIR-V/specs/unified1/OpenCL.ExtendedInstructionSet.100.html
Not sure though if GPU RT already supports it.
If it is supported, then perhaps it could emulate rol/ror for int64 even when HW doesn't support it.
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Not sure about about 2nd point : any combination of 16 bit and 32 bits arguments works for me without any issues.
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The failed tests are unrelated and already fixed by other commits in llvm-test-suite: Failed Tests (1): |
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