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[SYCL][ESIMD] Limit allowed argument types for rol/ror functions #6569

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Merged
merged 3 commits into from
Aug 23, 2022
Merged

[SYCL][ESIMD] Limit allowed argument types for rol/ror functions #6569

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e5c6431
Limit allowed argument types for rol/ror functions
fineg74 Aug 11, 2022
78e98e5
Add support for 64 bit arguments for PVC platform
fineg74 Aug 15, 2022
913908f
Enable 64 bit types for all platforms
fineg74 Aug 16, 2022
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82 changes: 52 additions & 30 deletions sycl/include/sycl/ext/intel/experimental/esimd/math.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -275,10 +275,13 @@ shr(T1 src0, T2 src1, Sat sat = {}) {
/// the input vector \p src0 shall be rotated.
/// @return vector of rotated elements.
template <typename T0, typename T1, int SZ>
__ESIMD_API
std::enable_if_t<std::is_integral<T0>::value && std::is_integral<T1>::value,
__ESIMD_NS::simd<T0, SZ>>
rol(__ESIMD_NS::simd<T1, SZ> src0, __ESIMD_NS::simd<T1, SZ> src1) {
__ESIMD_API std::enable_if_t<
__ESIMD_NS::detail::is_type<T0, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T1, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>(),
__ESIMD_NS::simd<T0, SZ>>
rol(__ESIMD_NS::simd<T1, SZ> src0, __ESIMD_NS::simd<T1, SZ> src1) {
return __esimd_rol<T0, T1, SZ>(src0.data(), src1.data());
}

Expand All @@ -291,10 +294,14 @@ __ESIMD_API
/// @param src1 the number of bit positions the input vector shall be rotated.
/// @return vector of rotated elements.
template <typename T0, typename T1, int SZ, typename U>
__ESIMD_API std::enable_if_t<std::is_integral<T0>::value &&
std::is_integral<T1>::value &&
std::is_integral<U>::value,
__ESIMD_NS::simd<T0, SZ>>
__ESIMD_API std::enable_if_t<
__ESIMD_NS::detail::is_type<T0, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T1, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<U, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>(),
__ESIMD_NS::simd<T0, SZ>>
rol(__ESIMD_NS::simd<T1, SZ> src0, U src1) {
__ESIMD_NS::simd<T1, SZ> Src1 = src1;
return esimd::rol<T0>(src0, Src1);
Expand All @@ -308,13 +315,17 @@ rol(__ESIMD_NS::simd<T1, SZ> src0, U src1) {
/// @param src1 the number of bit positions the input vector shall be rotated.
/// @return rotated left value.
template <typename T0, typename T1, typename T2>
__ESIMD_API std::enable_if_t<__ESIMD_DNS::is_esimd_scalar<T0>::value &&
__ESIMD_DNS::is_esimd_scalar<T1>::value &&
__ESIMD_DNS::is_esimd_scalar<T2>::value &&
std::is_integral<T0>::value &&
std::is_integral<T1>::value &&
std::is_integral<T2>::value,
std::remove_const_t<T0>>
__ESIMD_API std::enable_if_t<
__ESIMD_DNS::is_esimd_scalar<T0>::value &&
__ESIMD_DNS::is_esimd_scalar<T1>::value &&
__ESIMD_DNS::is_esimd_scalar<T2>::value &&
__ESIMD_NS::detail::is_type<T0, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T1, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T2, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>(),
std::remove_const_t<T0>>
rol(T1 src0, T2 src1) {
__ESIMD_NS::simd<T1, 1> Src0 = src0;
__ESIMD_NS::simd<T0, 1> Result = esimd::rol<T0, T1, 1, T2>(Src0, src1);
Expand All @@ -330,10 +341,13 @@ rol(T1 src0, T2 src1) {
/// the input vector \p src0 shall be rotated.
/// @return vector of rotated elements.
template <typename T0, typename T1, int SZ>
__ESIMD_API
std::enable_if_t<std::is_integral<T0>::value && std::is_integral<T1>::value,
__ESIMD_NS::simd<T0, SZ>>
ror(__ESIMD_NS::simd<T1, SZ> src0, __ESIMD_NS::simd<T1, SZ> src1) {
__ESIMD_API std::enable_if_t<
__ESIMD_NS::detail::is_type<T0, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T1, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>(),
__ESIMD_NS::simd<T0, SZ>>
ror(__ESIMD_NS::simd<T1, SZ> src0, __ESIMD_NS::simd<T1, SZ> src1) {
return __esimd_ror<T0, T1, SZ>(src0.data(), src1.data());
}

Expand All @@ -346,10 +360,14 @@ __ESIMD_API
/// @param src1 the number of bit positions the input vector shall be rotated.
/// @return vector of rotated elements.
template <typename T0, typename T1, int SZ, typename U>
__ESIMD_API std::enable_if_t<std::is_integral<T0>::value &&
std::is_integral<T1>::value &&
std::is_integral<U>::value,
__ESIMD_NS::simd<T0, SZ>>
__ESIMD_API std::enable_if_t<
__ESIMD_NS::detail::is_type<T0, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T1, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<U, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>(),
__ESIMD_NS::simd<T0, SZ>>
ror(__ESIMD_NS::simd<T1, SZ> src0, U src1) {
__ESIMD_NS::simd<T1, SZ> Src1 = src1;
return esimd::ror<T0>(src0, Src1);
Expand All @@ -363,13 +381,17 @@ ror(__ESIMD_NS::simd<T1, SZ> src0, U src1) {
/// @param src1 the number of bit positions the input vector shall be rotated.
/// @return rotated right value.
template <typename T0, typename T1, typename T2>
__ESIMD_API std::enable_if_t<__ESIMD_DNS::is_esimd_scalar<T0>::value &&
__ESIMD_DNS::is_esimd_scalar<T1>::value &&
__ESIMD_DNS::is_esimd_scalar<T2>::value &&
std::is_integral<T0>::value &&
std::is_integral<T1>::value &&
std::is_integral<T2>::value,
std::remove_const_t<T0>>
__ESIMD_API std::enable_if_t<
__ESIMD_DNS::is_esimd_scalar<T0>::value &&
__ESIMD_DNS::is_esimd_scalar<T1>::value &&
__ESIMD_DNS::is_esimd_scalar<T2>::value &&
__ESIMD_NS::detail::is_type<T0, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T1, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>() &&
__ESIMD_NS::detail::is_type<T2, int16_t, uint16_t, int32_t, uint32_t,
int64_t, uint64_t>(),
std::remove_const_t<T0>>
ror(T1 src0, T2 src1) {
__ESIMD_NS::simd<T1, 1> Src0 = src0;
__ESIMD_NS::simd<T0, 1> Result = esimd::ror<T0, T1, 1, T2>(Src0, src1);
Expand Down