Support for i7-1165G7

[curiousercreative]

Error: unsupported processor. Only Intel(R) processors are supported (Atom(R) and microarchitecture codename Nehalem/Nehalem-EP, Atom(tm), Westmere/Clarkdale, Sandy Bridge, Westmere-EP, Sandy Bridge-EP/Jaketown, Nehalem-EX, Westmere-EX, unknown, Centerton, Baytrail, Ivy Bridge, Haswell, Broadwell, Ivy Bridge-EP/EN/EX/Ivytown, Haswell-EP/EN/EX, Cherrytrail, Avoton, Broadwell-EP/EX, Skylake-SP, Cascade Lake-SP, Broadwell-DE, Knights Landing, Apollo Lake, Skylake, Denverton, Icelake, Kabylake). CPU model number: 140 Brand: "11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz"

[opcm]

@curiousercreative thank you very much for reporting this issue. We need some help from you to add support for this CPU. Could you please as an experiment replace "ICL = 126," with "ICL = 140," here:

https://github.com/opcm/pcm/blob/0a178ec2573821e3c08beb6bd76808ebb912bc76/cpucounters.h#L1247

Please recompile and share the output of pcm.x on your system with the change above.

Thank you in advance

[curiousercreative]

@opcm I ran pcm-power.x before this and it asked that I modprobe msr, so this is the output after recompiling and enabling that module.

# ./pcm.x

 Processor Counter Monitor  (2020-11-27 18:45:10 +0100 ID=1b0e45e)


Linux arch_perfmon flag  : yes
IBRS and IBPB supported  : yes
STIBP supported          : yes
Spec arch caps supported : yes
Number of physical cores: 4
Number of logical cores: 8
Number of online logical cores: 8
Threads (logical cores) per physical core: 2
Num sockets: 1
Physical cores per socket: 4
Core PMU (perfmon) version: 5
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 4
Width of fixed counters: 48 bits
Nominal core frequency: 2800000000 Hz
IBRS enabled in the kernel   : yes
STIBP enabled in the kernel  : no
The processor is not susceptible to Rogue Data Cache Load: yes
The processor supports enhanced IBRS                     : yes
Package thermal spec power: 28 Watt; Package minimum power: 0 Watt; Package maximum power: 0 Watt;
Trying to use Linux perf events...
Successfully programmed on-core PMU using Linux perf

Detected 11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz "Intel(r) microarchitecture codename Icelake" stepping 1 microcode level 0x6e

EXEC  : instructions per nominal CPU cycle
 IPC   : instructions per CPU cycle
 FREQ  : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
 AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state'  (includes Intel Turbo Boost)
 L3MISS: L3 (read) cache misses 
 L2MISS: L2 (read) cache misses (including other core's L2 cache *hits*) 
 L3HIT : L3 (read) cache hit ratio (0.00-1.00)
 L2HIT : L2 cache hit ratio (0.00-1.00)
 L3MPI : number of L3 (read) cache misses per instruction
 L2MPI : number of L2 (read) cache misses per instruction
 READ  : bytes read from main memory controller (in GBytes)
 WRITE : bytes written to main memory controller (in GBytes)
 IO    : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
 TEMP  : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
 energy: Energy in Joules


 Core (SKT) | EXEC | IPC  | FREQ  | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3MPI | L2MPI |  TEMP

   0    0     0.01   0.44   0.02    0.51      50 K    128 K    0.56    0.46    0.00    0.00     48
   1    0     0.02   0.24   0.07    0.47     272 K    531 K    0.48    0.33    0.01    0.01     48
   2    0     0.16   1.51   0.10    0.88      96 K    283 K    0.63    0.84    0.00    0.00     43
   3    0     0.07   1.58   0.04    0.70      86 K    164 K    0.46    0.84    0.00    0.00     43
   4    0     0.01   0.57   0.02    0.54      69 K    149 K    0.46    0.46    0.00    0.00     43
   5    0     0.00   0.38   0.01    0.47      27 K     73 K    0.57    0.34    0.00    0.01     43
   6    0     0.01   0.55   0.02    0.48      44 K    110 K    0.54    0.38    0.00    0.00     45
   7    0     0.03   0.97   0.03    0.70      29 K     92 K    0.64    0.86    0.00    0.00     45
---------------------------------------------------------------------------------------------------------------
 SKT    0     0.04   0.97   0.04    0.62     677 K   1535 K    0.52    0.70    0.00    0.00     40
---------------------------------------------------------------------------------------------------------------
 TOTAL  *     0.04   0.97   0.04    0.62     677 K   1535 K    0.52    0.70    0.00    0.00     N/A

 Instructions retired:  856 M ; Active cycles:  886 M ; Time (TSC): 2803 Mticks ; C0 (active,non-halted) core residency: 6.34 %

 C1 core residency: 11.64 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 82.02 %;
 C0 package residency: 49.57 %; C2 package residency: 30.61 %; C3 package residency: 19.81 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %; C8 package residency: 0.00 %; C9 package residency: 0.00 %; C10 package residency: 0.00 %;
                             
 Core    C-state distribution│00000111111111777777777777777777777777777777777777777777777777777777777777777777│
                             
 Package C-state distribution│00000000000000000000000000000000000000002222222222222222222222223333333333333333│

 PHYSICAL CORE IPC                 : 1.93 => corresponds to 48.29 % utilization for cores in active state
 Instructions per nominal CPU cycle: 0.08 => corresponds to 1.91 % core utilization over time interval
 SMI count: 0
---------------------------------------------------------------------------------------------------------------
MEM (GB)->|  READ |  WRITE |   IO   | CPU energy |
---------------------------------------------------------------------------------------------------------------
 SKT   0     0.00     0.00     0.00       4.32              
-------------------------------------------------------------------------------

[opcm]

@curiousercreative thanks a lot for this experiment. You can use the patched pcm and soon we will implement a more robust code change. pcm-power can't be supported on your CPU for the reasons described in FAQ Q5 but you can get some of the metrics in pcm.x, for example, the CPU energy metric.

[opcm]

@curiousercreative the cpu model has been added in the recent master branch and https://github.com/opcm/pcm/releases/tag/202101 release

[curiousercreative]

@opcm confirming pcm.x works fine now. Most of the programs still don't run and I imagine the hardware just doesn't support many of them, but some I suspect could be supported and in particular pcm-memory.x.

[opcm]

@curiousercreative thank you for the verification. And you are right, the hardware just does not have the corresponding monitoring units. This also applies to pcm-memory: https://github.com/opcm/pcm/blob/master/FAQ.md#q6

[curiousercreative]

ah, fair enough - thank you!