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edwarddavidbaker merged 6 commits into from
Jun 2, 2026
Merged

GNR, EMR, PTL, ARL, LNL: Release event updates #369

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b84e756
ARL: Release v1.19 event files
edwarddavidbaker Jun 2, 2026
3f1d40d
EMR: Release v1.24 event files
edwarddavidbaker Jun 2, 2026
875354c
GNR: Release v1.19 event files
edwarddavidbaker Jun 2, 2026
5535a3e
LNL: Release v1.25 event files
edwarddavidbaker Jun 2, 2026
ffc03fc
PTL: Release v1.06 event files
edwarddavidbaker Jun 2, 2026
9d61495
mapfile: Add PTL experimental uncore references
edwarddavidbaker Jun 2, 2026
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861 changes: 741 additions & 120 deletions ARL/events/arrowlake_crestmont_core.json
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126 changes: 63 additions & 63 deletions ARL/events/arrowlake_lioncove_core.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17",
"DatePublished": "02/26/2026",
"Version": "1.17",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19",
"DatePublished": "04/17/2026",
"Version": "1.19",
"Legend": ""
},
"Events": [
Expand Down Expand Up @@ -5436,11 +5436,11 @@
},
{
"EventCode": "0xc4",
"UMask": "0x01",
"UMask": "0x00",
"UMaskExt": "0x01",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"BriefDescription": "Taken conditional branch instructions retired.",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
"BriefDescription": "Taken forward conditional branch instructions retired.",
"PublicDescription": "Counts taken forward conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
Expand All @@ -5464,10 +5464,10 @@
{
"EventCode": "0xc4",
"UMask": "0x01",
"UMaskExt": "0x00",
"EventName": "BR_INST_RETIRED.COND_TAKEN_BWD",
"BriefDescription": "Taken backward conditional branch instructions retired.",
"PublicDescription": "Counts taken backward conditional branch instructions retired.",
"UMaskExt": "0x01",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"BriefDescription": "Taken conditional branch instructions retired.",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
Expand All @@ -5490,14 +5490,14 @@
},
{
"EventCode": "0xc4",
"UMask": "0x02",
"UMask": "0x01",
"UMaskExt": "0x00",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"BriefDescription": "Direct and indirect near call instructions retired.",
"PublicDescription": "Counts both direct and indirect near call instructions retired.",
"EventName": "BR_INST_RETIRED.COND_TAKEN_BWD",
"BriefDescription": "Taken backward conditional branch instructions retired.",
"PublicDescription": "Counts taken backward conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "100007",
"SampleAfterValue": "400009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
Expand All @@ -5518,13 +5518,13 @@
{
"EventCode": "0xc4",
"UMask": "0x02",
"UMaskExt": "0x01",
"EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
"BriefDescription": "Taken forward conditional branch instructions retired.",
"PublicDescription": "Counts taken forward conditional branch instructions retired.",
"UMaskExt": "0x00",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"BriefDescription": "Direct and indirect near call instructions retired.",
"PublicDescription": "Counts both direct and indirect near call instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
"SampleAfterValue": "100007",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
Expand Down Expand Up @@ -5814,18 +5814,18 @@
},
{
"EventCode": "0xc5",
"UMask": "0x01",
"UMaskExt": "0x80",
"EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST",
"BriefDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"UMask": "0x02",
"UMaskExt": "0x00",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"BriefDescription": "Mispredicted indirect CALL retired.",
"PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
"CollectPEBSRecord": "3",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
Expand All @@ -5841,14 +5841,14 @@
},
{
"EventCode": "0xc5",
"UMask": "0x02",
"UMask": "0x08",
"UMaskExt": "0x00",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"BriefDescription": "Mispredicted indirect CALL retired.",
"PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
"EventName": "BR_MISP_RETIRED.RET",
"BriefDescription": "This event counts the number of mispredicted ret instructions retired.",
"PublicDescription": "This event counts the number of mispredicted ret instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
"SampleAfterValue": "100007",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
Expand All @@ -5868,18 +5868,18 @@
},
{
"EventCode": "0xc5",
"UMask": "0x02",
"UMaskExt": "0x80",
"EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST",
"BriefDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"UMask": "0x10",
"UMaskExt": "0x00",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
"PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
"CollectPEBSRecord": "3",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
Expand All @@ -5895,14 +5895,14 @@
},
{
"EventCode": "0xc5",
"UMask": "0x08",
"UMaskExt": "0x00",
"EventName": "BR_MISP_RETIRED.RET",
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
"UMask": "0x11",
"UMaskExt": "0x01",
"EventName": "BR_MISP_RETIRED.COND",
"BriefDescription": "Mispredicted conditional branch instructions retired.",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "100007",
"SampleAfterValue": "400009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
Expand All @@ -5922,11 +5922,11 @@
},
{
"EventCode": "0xc5",
"UMask": "0x10",
"UMask": "0x20",
"UMaskExt": "0x00",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
"PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
Expand All @@ -5949,18 +5949,18 @@
},
{
"EventCode": "0xc5",
"UMask": "0x11",
"UMask": "0x40",
"UMaskExt": "0x01",
"EventName": "BR_MISP_RETIRED.COND",
"BriefDescription": "Mispredicted conditional branch instructions retired.",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST",
"BriefDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
"CollectPEBSRecord": "2",
"CollectPEBSRecord": "3",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
Expand All @@ -5976,18 +5976,18 @@
},
{
"EventCode": "0xc5",
"UMask": "0x20",
"UMaskExt": "0x00",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"UMask": "0x41",
"UMaskExt": "0x01",
"EventName": "BR_MISP_RETIRED.COND_TAKEN_COST",
"BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "1",
"CollectPEBSRecord": "2",
"CollectPEBSRecord": "3",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
Expand All @@ -6004,10 +6004,10 @@
{
"EventCode": "0xc5",
"UMask": "0x41",
"UMaskExt": "0x01",
"EventName": "BR_MISP_RETIRED.COND_TAKEN_COST",
"BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"UMaskExt": "0x00",
"EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST",
"BriefDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "400009",
Expand Down
8 changes: 4 additions & 4 deletions ARL/events/arrowlake_skymont_core.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17",
"DatePublished": "02/26/2026",
"Version": "1.17",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19",
"DatePublished": "04/17/2026",
"Version": "1.19",
"Legend": ""
},
"Events": [
Expand Down Expand Up @@ -1740,7 +1740,7 @@
"UMask": "0x00",
"UMaskExt": "0x00",
"EventName": "CORE_REJECT_L2Q.ANY",
"BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
"BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.",
"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
"Counter": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3,4,5,6,7",
Expand Down
6 changes: 3 additions & 3 deletions ARL/events/arrowlake_uncore.json
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@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17",
"DatePublished": "02/26/2026",
"Version": "1.17",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19",
"DatePublished": "04/17/2026",
"Version": "1.19",
"Legend": ""
},
"Events": [
Expand Down
6 changes: 3 additions & 3 deletions ARL/events/arrowlake_uncore_experimental.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17",
"DatePublished": "02/26/2026",
"Version": "1.17",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19",
"DatePublished": "04/17/2026",
"Version": "1.19",
"Legend": ""
},
"Events": [
Expand Down
31 changes: 28 additions & 3 deletions EMR/events/emeraldrapids_core.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.23",
"DatePublished": "02/20/2026",
"Version": "1.23",
"Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.24",
"DatePublished": "05/19/2026",
"Version": "1.24",
"Legend": ""
},
"Events": [
Expand Down Expand Up @@ -2232,6 +2232,31 @@
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x42",
"UMask": "0x02",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"BriefDescription": "Cycles when L1D is locked",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "0",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x43",
"UMask": "0xfd",
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6 changes: 3 additions & 3 deletions EMR/events/emeraldrapids_uncore.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.23",
"DatePublished": "02/20/2026",
"Version": "1.23",
"Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.24",
"DatePublished": "05/19/2026",
"Version": "1.24",
"Legend": ""
},
"Events": [
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6 changes: 3 additions & 3 deletions EMR/events/emeraldrapids_uncore_experimental.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.23",
"DatePublished": "02/20/2026",
"Version": "1.23",
"Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.24",
"DatePublished": "05/19/2026",
"Version": "1.24",
"Legend": ""
},
"Events": [
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6 changes: 3 additions & 3 deletions GNR/events/graniterapids_core.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.18",
"DatePublished": "04/09/2026",
"Version": "1.18",
"Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.19",
"DatePublished": "04/23/2026",
"Version": "1.19",
"Legend": ""
},
"Events": [
Expand Down
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