v0.2.1

What's Changed

• update deployment workflow to install SystemVerilog to Verilog conver… by @desmonddak in #224
• updated broken html links in markdown by @desmonddak in #226
• fix just the deprecated Port calls to Logic.port by @desmonddak in #231
• migrated to new Yosys and removed sv2v by @desmonddak in #229
• Multiplier doc by @desmonddak in #219
• Serializer doc link by @desmonddak in #220
• fix proper quotations of classes and literals true and false by @desmonddak in #223
• fix for MAC trace error by @desmonddak in #240
• bug in DAZ computing effectiveSubtraction incorrectly by @desmonddak in #239
• add definitionName to all components and update configurator/markdown… by @desmonddak in #227
• Fix signal names by @desmonddak in #237
• fix count internal naming by @desmonddak in #244
• update Interface classes to include the required clone() method. by @desmonddak in #245
• convert a boolean signExtend to a runtime or static parameter by @desmonddak in #246
• dot-product-component by @desmonddak in #243
• Resettable entries by @mkorbel1 in #253
• Enable Fifo to return the same type as was received by @mkorbel1 in #254
• Floating Point Value operations: negation and comparison by @desmonddak in #232
• changelog entries for 0.2.1 release by @desmonddak in #261

Full Changelog: v0.2.0...v0.2.1