Adding mechanisms to remove redundant parentheses. #586
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mkorbel1
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Mar 10, 2025
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mkorbel1
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mkorbel1
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See notes in #584 (review), which applies to this PR as well
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I think this PR is not on a trend where it will be merged into ROHD, so I'm closing it. Thank you for the time you've spent on this, and the original issue is still worth addressing, but this approach isn't quite right. If you'd like to continue on this development with an adjusted approach, we can either re-open this PR or open a new one. |
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Description & Motivation
There are cases where generated SystemVerilog code has too many parentheses to increase safety, ensure order of operations and matching the generated intent. This changes add mechanisms to identify redundancies with parenthesis and remove them to simplify the generated code.
Related Issue(s)
#552
Testing
A unit testing script was created to validate the [RedundancyHandler] functionality.
rohd/test/redundancy_handler_test.dart
Backwards-compatibility
No.
Documentation
The [RedundancyHandler] class was added with its code documentation, no need to add more.
rohd/lib/src/utilities/redundancy_handler.dart