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Description & Motivation
There was a bug where if an
inOutlooped back onto the same module, and the intermediate signal(s) were not named (mergeable or less), then the generated SystemVerilog could have incorrectly pruned that signal and left both ports unconnected. This PR fixes the bug.Related Issue(s)
N/A
Testing
Added new test and existing tests cover other stuff.
Backwards-compatibility
No
Documentation
No