8-Bit Arithmetic Logic Unit (ALU) Implementation 💾

CURRENTLY LOOKING TO IMPLEMENT VEDIC MATHEMATICS TO IT (WE WILL LOVE A GOOD PR 💗)

Overview 📝

This project implements an 8-bit Arithmetic Logic Unit (ALU) using Verilog, along with a testbench to verify its functionality. The ALU performs common arithmetic (addition, subtraction) and logic (AND, OR, XOR, NAND, NOR, XNOR) operations on two 8-bit input buses based on selection inputs.

Prerequisites 🛠️

• Verilog compiler (e.g., Icarus Verilog)
• Simulation tool (e.g., GTKWave)
• Python (for input handling)

Running the Simulation ▶️

1. Clone the repository:

   git clone https://github.com/not-adarsh/ArithematicLogicalUnit.git

2. In case you are using Icarus Verilog:

   • Move this folder to C:/iverilog/bin folder on Windows.
   • Move this folder to usr/iverilog/bin folder on Linux.

3. Navigate to the project directory:

   cd ArithematicLogicalUnit

4. Run the Python script to compile and simulate the Verilog code:

   python main.py

Contributors 👥

• Adarsh
• Yashvardhan Dhaka
• Arindam Singh
• Kavit Shukla
• Saksham Gupta

GitHub Repository 🌐

ArithematicLogicalUnit

REFERENCE ℹ️

For more detailed documentation, please refer to this Google Docs document.