riscv

RISCV CPU implementation. Starting with 5 stage pipelined CPU, and the goal of making it more modern with cache, multicore, multithread, OOP and anything else we find out goes into making it modern.

Authors: James, Ezequiel

To Do

Basic Implementation:

• Read the 32 bit unpriviliged instruction set.
• Implemente a 5 stage pipelined CPU Furture Implementation:
• Implement the 64 bit priviliged.

Notes

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