GitHub - jeffriblr2/UART-design: Implemented a programmable UART IP module on Cyclone V FPGA which is capable of being controlled from the hard processor subsystem over an Avalon memory mapped interface using Linux kernel modules.

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Implemented a programmable UART IP module on Cyclone V FPGA which is capable of being controlled from the hard processor subsystem over an Avalon memory mapped interface using Linux kernel modules.

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
.cproject		.cproject
.project		.project
ClockGenNm.v		ClockGenNm.v
FIFO.v		FIFO.v
address_map.h		address_map.h
c5_pin_model_dump.txt		c5_pin_model_dump.txt
cleanup.sh		cleanup.sh
dividex16.v		dividex16.v
dividex16.v.bak		dividex16.v.bak
gpio.v		gpio.v
gpio_hw.tcl		gpio_hw.tcl
hps_sdram_p0_summary.csv		hps_sdram_p0_summary.csv
read_write.c		read_write.c
receiver.v		receiver.v
soc_system.asm.rpt		soc_system.asm.rpt
soc_system.cdf		soc_system.cdf
soc_system.done		soc_system.done
soc_system.eda.rpt		soc_system.eda.rpt
soc_system.fit.rpt		soc_system.fit.rpt
soc_system.fit.smsg		soc_system.fit.smsg
soc_system.fit.summary		soc_system.fit.summary
soc_system.flow.rpt		soc_system.flow.rpt
soc_system.jdi		soc_system.jdi
soc_system.map.rpt		soc_system.map.rpt
soc_system.map.smsg		soc_system.map.smsg
soc_system.map.summary		soc_system.map.summary
soc_system.pin		soc_system.pin
soc_system.qpf		soc_system.qpf
soc_system.qsf		soc_system.qsf
soc_system.qsys		soc_system.qsys
soc_system.qws		soc_system.qws
soc_system.sld		soc_system.sld
soc_system.sof		soc_system.sof
soc_system.sopcinfo		soc_system.sopcinfo
soc_system.sta.rpt		soc_system.sta.rpt
soc_system.sta.summary		soc_system.sta.summary
soc_system.tcl		soc_system.tcl
soc_system_assignment_defaults.qdf		soc_system_assignment_defaults.qdf
soc_system_timing.sdc		soc_system_timing.sdc
top.v		top.v
top.v.bak		top.v.bak
transmitter.v		transmitter.v
transmitter.v.bak		transmitter.v.bak
uart.v		uart.v
uart_hw.tcl		uart_hw.tcl
uart_hw.tcl~		uart_hw.tcl~
uart_ip.c		uart_ip.c
uart_ip.h		uart_ip.h
uart_regs.h		uart_regs.h

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Implemented a programmable UART IP module on Cyclone V FPGA which is capable of being controlled from the hard processor subsystem over an Avalon memory mapped interface using Linux kernel modules.