Semihost extended exit and More floating point support (VABS, VCMP, VMRS) #51
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…nce VMRS instruction decoding Fix bugs in VLDR, VMOV. Add test cases.
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This pull request includes several changes across different files to enhance functionality, improve code structure, and update test scripts. The most important changes include modifying return types and error handling in
src/main.rs, adding new floating-point register operations, and updating test scripts for better error handling and documentation.Modifications to return types and error handling:
src/main.rs: Changed the return type ofrun_binandrunfunctions fromResult<()>toResult<u32>, and updated themainfunction to handle the new return type and exit with the appropriate code. [1] [2] [3] [4] [5] [6]Enhancements to floating-point operations:
src/semihost.rs: Added handling forSysExitExtendedcommand with subcode and exit code.zmu_cortex_m/src/core/fpregister.rs: Introduced a new traitFpscrfor accessing and modifying floating-point status and control register flags.Updates to test scripts:
test_gcc.sh: Rearranged the order of GCC tests, added error handling to abort on test failure, and improved the output for better readability. [1] [2]tests/instruction-test-bench/main.c: Added detailed comments and new test cases for ARM Cortex-M instructions, including floating-point operations. [1] [2] [3]Code structure improvements:
zmu_cortex_m/src/core/instruction.rs: Added new instruction parameters and restructured theInstructionenum to better organize multiply and saturating instructions. [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]Miscellaneous changes:
zmu.code-workspace: Updated workspace settings to associateassert.hwith the C language.zmu_cortex_m/build.rs: Enabled additional floating-point instruction decoding.zmu_cortex_m/src/core/exception.rs: Simplified the handling of the processor's sleeping state. [1] [2]