Skip to content
View johnbagshaw007's full-sized avatar

Block or report johnbagshaw007

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
johnbagshaw007/README.md
  • 👋 Hi, I’m John Bagshaw - hardware design and software development expert
  • 👀 I’m interested in FPGA/SoC designs, C++, Python, Verilog, SystemVerilog, UVM, ML/AI/Data Science and chatbots
  • 🌱 I currently have over 6 years of experience in the aforementioned domains
  • 💞️ I’m looking to collaborate on related projects
  • 📫 How to reach me: johnbagshaw007@gmail.com and https://www.linkedin.com/in/jotshaw/

Popular repositories Loading

  1. PythonProjects PythonProjects Public

    Projects in Python from fundamentals to real-world project - Python encyclopedia

    Python 1

  2. johnbagshaw007 johnbagshaw007 Public

    Config files for my GitHub profile.

  3. FPGA-SoC FPGA-SoC Public

    Verilog

  4. HLS_FPGA_embeddedSystems HLS_FPGA_embeddedSystems Public

    C++