GitHub - jschein01/EE469Schein: Archive of my computer arch class

This is an archive of my final project for my computer architecture course at UW

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
adder64.sv		adder64.sv
adder64.sv.bak		adder64.sv.bak
adder64_wave.do		adder64_wave.do
alu.sv		alu.sv
alu.sv.bak		alu.sv.bak
alu_wave.do		alu_wave.do
alustim.sv		alustim.sv
bitALU.sv		bitALU.sv
bitALU.sv.bak		bitALU.sv.bak
bitALU_wave.do		bitALU_wave.do
bookmarks.do		bookmarks.do
controlUnit.sv		controlUnit.sv
controlUnit.sv.bak		controlUnit.sv.bak
controlUnit_wave.do		controlUnit_wave.do
datamem.sv		datamem.sv
enD_FF.sv		enD_FF.sv
enDec2_4.sv		enDec2_4.sv
enDec3_8.sv		enDec3_8.sv
enDec5_32.sv		enDec5_32.sv
execute.sv		execute.sv
execute.sv.bak		execute.sv.bak
flagReg.sv		flagReg.sv
flagReg.sv.bak		flagReg.sv.bak
forwardingUnit.sv		forwardingUnit.sv
forwardingUnit.sv.bak		forwardingUnit.sv.bak
fullAdder.sv		fullAdder.sv
fullAdder.sv.bak		fullAdder.sv.bak
fullAdder_wave.do		fullAdder_wave.do
fullDatapath.sv		fullDatapath.sv
fullDatapath.sv.bak		fullDatapath.sv.bak
instructionFetch.sv		instructionFetch.sv
instructionFetch.sv.bak		instructionFetch.sv.bak
instructionFetch_wave.do		instructionFetch_wave.do
instructmem.sv		instructmem.sv
instructmem.sv.bak		instructmem.sv.bak
instructmem_wave.do		instructmem_wave.do
lab_wave.do		lab_wave.do
math.sv		math.sv
memStage.sv		memStage.sv
memStage.sv.bak		memStage.sv.bak
mux2_1.sv		mux2_1.sv
mux2_1.sv.bak		mux2_1.sv.bak
mux2_1_wave.do		mux2_1_wave.do
mux2_1x64.sv		mux2_1x64.sv
mux2_1x64.sv.bak		mux2_1x64.sv.bak
mux2_1x64_wave.do		mux2_1x64_wave.do
mux32_1.sv		mux32_1.sv
mux4_1.sv		mux4_1.sv
mux8_1.sv		mux8_1.sv
mux8_1.sv.bak		mux8_1.sv.bak
muxArr64x32_1.sv		muxArr64x32_1.sv
pipeLinedMachine.sv		pipeLinedMachine.sv
pipeLinedMachine.sv.bak		pipeLinedMachine.sv.bak
programCounter.sv.bak		programCounter.sv.bak
programCounter_wave.do		programCounter_wave.do
regDecode.sv		regDecode.sv
regDecode.sv.bak		regDecode.sv.bak
regfile.sv		regfile.sv
regfile.sv.bak		regfile.sv.bak
register.sv		register.sv
register.sv.bak		register.sv.bak
regstim.sv		regstim.sv
run2_1Mux.do		run2_1Mux.do
run2_1Muxx64.do		run2_1Muxx64.do
runAdd.do		runAdd.do
runAdder64.do		runAdder64.do
runAlu.do		runAlu.do
runControlUnit.do		runControlUnit.do
runInstructMem.do		runInstructMem.do
runInstructionFetch.do		runInstructionFetch.do
runProgramCounter.do		runProgramCounter.do
runSignExtend19.do		runSignExtend19.do
runZeros.do		runZeros.do
runbitALU.do		runbitALU.do
runlab.do		runlab.do
shift2.sv		shift2.sv
shift2.sv.bak		shift2.sv.bak
signExtend.sv		signExtend.sv
signExtend.sv.bak		signExtend.sv.bak
signExtend19_64.sv		signExtend19_64.sv
signExtend19_64.sv.bak		signExtend19_64.sv.bak
signExtend_wave.do		signExtend_wave.do
singleCycleMachine.sv.bak		singleCycleMachine.sv.bak
test01_AddiB.arm		test01_AddiB.arm
test02_AddsSubs.arm		test02_AddsSubs.arm
test03_CbzB.arm		test03_CbzB.arm
test04_LdurStur.arm		test04_LdurStur.arm
test05_Blt.arm		test05_Blt.arm
test06_MulLslLsr.arm		test06_MulLslLsr.arm
test10_forwarding.arm		test10_forwarding.arm
test11_Sort.arm		test11_Sort.arm
test12_Division.arm		test12_Division.arm
writeBack.sv		writeBack.sv
zeroFlag.sv		zeroFlag.sv
zeroFlag.sv.bak		zeroFlag.sv.bak
zeroFlag_wave.do		zeroFlag_wave.do
zeros.sv.bak		zeros.sv.bak

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