A-Simple-Digital-Filter

This repository contains a complete implementation of a custom digital filter in VHDL, along with documentation and source code.

📁 Repository Structure

• code/ - Contains all VHDL source files and detailed README

  • README.md - Complete technical documentation with code explanations
  • filter.vhdl - Top-level design file
  • cu.vhdl - Control unit implementation
  • ...and other VHDL components

• images/ - Contains all diagrams and simulation results

  • Architecture diagrams
  • Simulation waveforms
  • Result plots

🚀 Quick Start

To dive into the project:

1. Check the detailed README in the code directory for a complete explanation of how the filter works
2. Explore the VHDL source files to understand the implementation
3. Review the images directory for visual explanations of the architecture and results

📊 Project Overview

This project implements a digital filter with the following transfer function:

Y(n) = -0.5X(n) - 2X(n-1) + 4X(n-2) + 0.25X(n-3)

Key features include:

• Hardware-efficient design using shift registers
• Optimized power-of-two coefficient implementation
• Full state machine controller
• Overflow detection and handling

📝 Project Overview

This project implements a custom digital filter in VHDL, designed to process a series of 1024 8-bit samples. The filter applies the following operation to each sample:

Y(n) = -0.5X(n) - 2X(n-1) + 4X(n-2) + 0.25X(n-3)

This digital filter demonstrates key concepts in digital signal processing, including shift registers, numerical optimization for hardware implementation, overflow detection, and state machine design.

🔍 Key Features

• Implementation of a custom digital filtering algorithm
• Efficient hardware design using shift registers
• Optimized bitwise operations to avoid complex multiplication units
• Overflow detection and handling
• Complete VHDL implementation with testbench
• Verified functionality through simulation

🧠 Design Approach

Smart Coefficient Implementation

Rather than implementing costly multipliers, this design uses power-of-two coefficients, allowing multiplication through simple bit shifting:

Coefficient	Implementation	Shift Register Type
-0.5	Right shift 1	LR, one step
-2	Left shift 1	RL, two steps
4	Left shift 2	RL, one step
0.25	Right shift 2	LR, four steps

Overflow Handling

The filter includes a sophisticated mechanism to detect overflow in 2's complement arithmetic, ensuring signal integrity by:

• Detecting overflow conditions using carry bits
• Clamping outputs to maximum/minimum values when overflow occurs
• Managing proper 2's complement representation throughout the pipeline

State Machine Controller

A Moore-type state machine drives the entire system through two main phases:

1. Sample Collection Phase: Loading 1024 samples into memory
2. Processing Phase: Filtering samples and storing results

💻 Implementation Details

Architecture

The system is organized into:

• Control Unit (CU): Manages the system state and control signals
• Datapath: Contains the filter implementation with shift registers and adders
• Memory Components: Two memory modules (mema and memb) for input and output data

Algorithm Flow

// Phase 1: Sample Collection
address = 0;
while address < 1024 do
  write datain @ address in mema
  address = address + 1;
end while;

// Phase 2: Sample Processing
address = 0;
while address < 1024 do
  read @ address in mema
  load shift register
  shift registers according to coefficients
  add contents with proper sign handling
  check for overflow conditions
  write result @ address in memb
  address = address + 1;
end while;

📁 Code Structure

The implementation is divided into several VHDL components:

• filter.vhdl: Top-level entity connecting all components
• cu.vhdl: Control unit implementing the state machine
• counter.vhdl: Address counter for memory access
• mema.vhdl: Input memory for storing samples
• memb.vhdl: Output memory for filtered data
• adder_4.vhdl: Component to sum the signal contributions
• Shift registers:
  • lrshift_reg.vhdl: Logical right shift register (for division)
  • rlshift_reg.vhdl: Left shift register (for multiplication)
  • lr4xshift_reg.vhdl: 4× right shift register
  • rl2xshift_reg.vhdl: 2× left shift register
• testbench.vhdl: Simulation environment to verify functionality

🔄 State Machine Design

The control unit follows this state diagram:

📊 Simulation Results

The design was verified through comprehensive simulation, with key checkpoints including:

Simulation showing the system initialization and the first control signals

Filter processing phase showing correct behavior

📈 Results

The filter demonstrated correct functionality in transforming the input signal:

Input test signal

Output result after filtering

🔧 Technical Implementation

The filter's pipeline timing diagram shows how samples flow through the system:

📚 Learning Outcomes

This project demonstrates several important concepts in digital design:

• Implementing mathematical functions in hardware
• Optimizing operations for digital logic
• Creating efficient state machines
• Managing memory operations in a pipelined fashion
• Signal overflow detection and handling

---

Developed by Lorenzo Germano (S246749)