[ImportVerilog] Add capture analysis pre-pass for functions by fabianschuiki · Pull Request #10094 · llvm/circt

fabianschuiki · 2026-04-01T03:41:17Z

Add a pre-pass over the slang AST that determines which non-local, non-global variables each function captures, either directly or transitively through calls. This walks the entire AST, collecting variable references and call graph edges, then propagates captures through the inverse call graph using a worklist until stable.

This analysis is a prerequisite for switching ImportVerilog to a two-phase declare-then-define approach for functions. Currently, function bodies are converted eagerly during package/module member iteration, which can fail when a function transitively references a variable that hasn't been declared yet (e.g., UVM's m_uvm_core_state). With the capture sets known upfront, function declarations can include the correct capture parameters from the start, and body conversion can be deferred.

Also add MapVector, SmallMapVector, and SmallSetVector re-exports.

The analysis is not yet directly used in ImportVerilog. This will be done in a follow-up commit.

uenoku

Not blocking at all but it’s a bit unfortunate that we have to run this level of analysis at the Slang AST. While the current complexity is manageable, if it continues to grow, I wonder if it's a good idea to introduce an intermediate operation to capture variables (e.g., a function-like operation without IsolatedFromAbove, maybe moore.closure) so we can progressively lower it.

fabianschuiki · 2026-04-01T17:31:28Z

@uenoku I went back and forth on this a bit. Intuitively, I thought lowering everything and then finding captured variables as SSA value uses that cross the function boundary sounded pretty good. But the problem with that is that we need to keep a map from AST nodes to SSA values around, instead of just keeping scoped hash maps and popping scopes as we leave them. That whole thing started to feel very ugly and messy compared to analyzing the captures at the frontend language level using the AST, and then just emitting the right IR for that directly 🤔

fabianschuiki · 2026-04-01T17:47:00Z

Thanks for the comments @uenoku -- I've addressed them 👍

fabianschuiki · 2026-04-01T18:17:27Z

Results of circt-tests run for 34ecdfc compared to results for 56e2170: no change to test results.

fabianschuiki · 2026-04-01T20:00:01Z

Results of circt-tests run for 17871eb compared to results for 56e2170: no change to test results.

Add a pre-pass over the slang AST that determines which non-local, non-global variables each function captures, either directly or transitively through calls. This walks the entire AST, collecting variable references and call graph edges, then propagates captures through the inverse call graph using a worklist until stable. This analysis is a prerequisite for switching ImportVerilog to a two-phase declare-then-define approach for functions. Currently, function bodies are converted eagerly during package/module member iteration, which can fail when a function transitively references a variable that hasn't been declared yet (e.g., UVM's `m_uvm_core_state`). With the capture sets known upfront, function declarations can include the correct capture parameters from the start, and body conversion can be deferred. Also add `MapVector`, `SmallMapVector`, and `SmallSetVector` re-exports. The analysis is not yet directly used in ImportVerilog. This will be done in a follow-up commit. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

uenoku · 2026-04-01T21:12:59Z

+
+/// Test fixture that skips all tests when running under Valgrind, since slang
+/// triggers Valgrind's uninitialized value detection.
+class CaptureAnalysisTest : public testing::Test {


fabianschuiki · 2026-04-01T21:31:56Z

Results of circt-tests run for 88297f5 compared to results for 56e2170: no change to test results.

Add a pre-pass over the slang AST that determines which non-local, non-global variables each function captures, either directly or transitively through calls. This walks the entire AST, collecting variable references and call graph edges, then propagates captures through the inverse call graph using a worklist until stable. This analysis is a prerequisite for switching ImportVerilog to a two-phase declare-then-define approach for functions. Currently, function bodies are converted eagerly during package/module member iteration, which can fail when a function transitively references a variable that hasn't been declared yet (e.g., UVM's `m_uvm_core_state`). With the capture sets known upfront, function declarations can include the correct capture parameters from the start, and body conversion can be deferred. Also add `MapVector`, `SmallMapVector`, and `SmallSetVector` re-exports. The analysis is not yet directly used in ImportVerilog. This will be done in a follow-up commit. Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

fabianschuiki requested review from Scheremo, TaoBi22, maerhart and uenoku April 1, 2026 03:41

fabianschuiki added the ImportVerilog label Apr 1, 2026