ARM branch instructions have inconsistent predicate operand placement

[llvmbot]

Bugzilla Link	10007
Version	trunk
OS	All
Reporter	LLVM Bugzilla Contributor
CC	@asl,@efriedma-quic,@rengolin

Extended Description

The ARM branch instructions have inconsistent predicate operand placement. BL/tBL want the predicate before the register operand; BX/tBX want it after the register operand; tBLXr wants it after, but tBLXr_r9 wants it before, etc.

[llvmbot]

Other examples can be found by doing disassembly of various thumb instructions to MCInsts where the destination is the 2nd operand instead of the first, or other unexpected ordering issues occur, with GPRs as well as predicates. I was never able to determine the reason behind this but it makes constructing instructions directly from the MC layer more complicated on ARM since they have to be looked up in tablegen or disassembled to MC first to determine proper operand order. It would be nice to see it fixed, but since this layer isn't exposed to the end user as an easily accessible API it also isn't a huge priority IMO. Making them consistent would change large chunks of the ARM backend for what probably amounts to little real gain.

[llvmbot]

Without a backend and tablegen re-write, fixing this at this point isn't reasonable IMO. Are there any objections to marking this WONTFIX?

CCing Renato